ADV
ANCEINFORMA
TION
33
SNAS724 – FEBRUARY 2018
Product Folder Links:
Copyright © 2018, Texas Instruments Incorporated
In 2-loop mode with the TCXO-DPLL, the REF-DPLL is not used and the TCXO-DPLL loop filter output directly
modulates the APLL NDIV MASH engine to steer the APLL VCO into lock with the TCXO input.
In 3-loop mode, the REF-DPLL loop filter output modulates the TCXO-DPLL FB_DIV MASH engine, and the
TCXO-DPLL loop filter output correspondingly modulates the APLL NDIV MASH engine to steer the APLL VCO
into lock with the selected REF-DPLL input.
9.3.8.12 REF-DPLL and TCXO-DPLL Feedback Dividers (FB_PRE_DIV, FB_DIV)
The feedback path of each REF-DPLL and TCXO-DPLL has an feedback prescaler (FB_PRE_DIV) followed by a
fractional feedback divider (FB_DIV). The FB_PRE_DIV divides its PLL primary post divider (P1) by a
programmable value from 2 to 17 and outputs the prescaler clock to the FB_DIV. The FB_DIV of each REF-
DPLL and TCXO-DPLL includes a 30-b integer portion (INT), 40-b numerator portion (NUM), and 40-b
denominator portion (DEN). The total FB_DIV value is: FB_DIV = INT + NUM / DEN. The FB_DIV output sets the
TDC rate to the respective DPLL.
9.3.8.13 PLL VCO Post Dividers (P1, P2)
Each PLL has a primary (P1) and secondary (P2) VCO post divider for more flexible clock frequency generation.
Each post divider supports divide by 4 to 9, 11, or 13 from the VCO frequency. Each post divider frequency for
PLL1 and PLL2 is distributed to the output block where it can be selected by any output channel mux. The P1
post divider output for each PLL is also fed-back to their respective REF-DPLL and TCXO-DPLL feedback divider
paths to close the loops.
Once the P1 divider and DPLL fractional feedback dividers have been configured for closed-loop operation, the
P1 divider should not be changed dynamically without also changing the DPLL feedback dividers to maintain the
original TDC rates. A software PLL reset is required after changing any PLL post divider value.
9.3.8.14 VCO Calibration
Each PLL's VCO must be calibrated to ensure that the clock outputs deliver optimal phase noise performance.
Fundamentally, a VCO calibration establishes an optimal operating point within the tuning range of the VCO.
While transparent to the user, the LMK05028 performs the following steps during a VCO calibration sequence:
1.
Normal Operation
– When the LMK05028 is in normal (operational) mode, the state of both the power-down
pin (PDN) is high.
2.
Entering the reset state
- If the user wishes to restore all device defaults and initiate a VCO calibration
sequence, then the host system must place the device in reset through the PDN pin, or through
programming, or by removing and restoring device power. Pulling the PDN pin low or through programming
places the device in the reset state.
3.
Exiting the reset state
– The device calibrates the VCO either by exiting the device reset state or through
the device reset command initiated through the host interface. Exiting the reset state occurs automatically
after power is applied, the system restores the state of the PDN, or both, or through programming from the
low to high state. Exiting the reset state using this method causes the device defaults to be loaded or
reloaded into the device register bank. Invoking a device reset through the register bit does not restore
device defaults; rather, the device retains settings related to the current clock frequency plan. Using this
method allows for a VCO calibration for a frequency plan other than the default state (that is, the device
calibrates the VCO based on the settings contained within the registers). The nominal state of this bit is low.
Writing this bit to a high state and then returning it to the low state invokes a device reset without restoring
device defaults.
4.
Device stabilization
– After exiting the reset state as described in Step 3, the device monitors internal
voltages and starts a reset timer. Only after internal voltages are at the correct level and the reset time has
expired will the device initiate a VCO calibration. This ensures that the device power supplies and phase
locked loops have stabilized prior to calibrating the VCO.
5.
VCO Calibration
– The LMK05028 calibrates the VCO. During the calibration routine, the device holds all
outputs in reset so that they generate no spurious clock signals.
9.3.9 Output Channel Muxes
Each of the 6 output channels has an output mux. The output muxes for outputs 2 to 7 can select between the
PLL1 and PLL2 post divider clocks. The output muxes for outputs 0 and 1 can select between PLL1 and PLL2
post divider clocks, XO input, or one of the reference bypass mux inputs.
Summary of Contents for LMK05028
Page 57: ......