ADV
ANCEINFORMA
TION
Is LOS (frequency,
missing pulse or amplitude monitor)
of selected input = 1?
Is holdover history valid?
Yes
Free-run mode
Holdover mode (locked to average tuning
word from history)
Yes
Locked State
No
Yes
Is LOS (frequency,
missing pulse or amplitude monitor)
of selected input = 1?
Lock Acquisition (Fastlock, Phase
Cancellation)
Is LOS (frequency,
missing pulse or amplitude monitor)
of selected input = 1?
Yes
No
No
Is DCO mode enabled?
Follow increment/decrement as per control pin
settings for each TCXO-DPLL
Yes
No
Is DCO mode enabled?
Follow increment/decrement as per control pin
settings for each TCXO-DPLL
Yes
No
No
37
SNAS724 – FEBRUARY 2018
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Copyright © 2018, Texas Instruments Incorporated
Device Functional Modes (continued)
9.4.2 Lock Acquisition Mode
Each DPLL constantly monitors its assigned inputs for a valid clock. When at least one valid clock is detected,
the DPLL will exit free-run or holdover mode and initiate lock acquisition. The LMK05028 supports a fast lock
feature where the loop bandwidth is set to wider than the nominal setting the during lock acquisition to reduce the
lock time. Once lock acquisition is done, the loop bandwidth is set to its nominal loop bandwidth setting.
9.4.3 Locked Mode
When a DPLL has completed lock acquisition, the PLL output clocks will be frequency and phase locked to its
selected input clock. While the DPLL is locked, the output clocks will not be affected by frequency drift on the XO
input or the TCXO input if the TCXO-DPLL is configured. Each DPLL has a programmable frequency and phase
lock detector thresholds to indicate DPLL lock status, which can be observed through status pin or interrupt
register bits.
9.4.4 Holdover Mode
If a tuning word history exists, the holdover frequency is the average frequency just prior to entry of the holdover.
If no tuning word history exists, the holdover frequency is determined by the free-run tuning word register (user
programmable). The initial holdover frequency accuracy depends on the loop bandwidth of the REF-DPLL and
the time elapsed to compute a tuning word history. In general, the longer the historical average, the more
accurate the initial holdover frequency (assuming the 0-ppm reference clock is drift-free). The stability of 0-ppm
reference clock (XO or TCXO input) determines the long-term stability and accuracy of the holdover output
frequency. Holdover mode flow chart is shown in
Figure 35. LMK05028 Holdover Flowchart
Summary of Contents for LMK05028
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