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ADV
ANCEINFORMA
TION
11
SNAS724 – FEBRUARY 2018
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Copyright © 2018, Texas Instruments Incorporated
1.8-V LVCMOS Output Characteristics (OUTx_P/N) (continued)
VDD = 3.3 V ± 5%, VDDO = 1.8 V ± 5%, T
A
= –40ºC to 85ºC, Fast slew rate
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
PN-Floor
Output phase noise floor
(f
OFFSET
= 10 MHz)
(1)
66.66 MHz
–155
dBc/Hz
ODC
Output duty cycle
(1)
Not PLL bypass output
45
55
%
R
OUT
Output impedance
50
Ω
(1)
Parameter is specified by characterization and is not tested in production.
(2)
An output frequency over the f
OUT
max spec is possible, but the output swing may be less than the V
OD
min spec.
7.12 AC-LVDS Output Characteristics (OUTx_P/N)
VDD = 3.3 V ± 5%, VDDO = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5%, T
A
= –40ºC to 85ºC, Output pair AC-coupled to 100-
Ω
differential load, Fast slew rate
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
f
OUT
Output frequency
(1) (2)
750
MHz
V
OD
Output voltage swing (V
OH
-
V
OL
)
f
OUT
≥
25 MHz
250
400
450
mV
V
ODpp
Differential output voltage
swing, peak-to-peak
2 × |V
OD
|
V
V
OS
Output common mode
100
430
mV
t
SKEW
Output-to-output skew
(1)
Same post divider, output divide values, and
output type
100
ps
t
R
/t
F
Output rise/fall time
(1)
20% to 80%, < 300 MHz
150
300
ps
±100 mV around center point, > 300 MHz
200
PN-Floor
Output phase noise floor
(f
OFFSET
= 10 MHz)
156.25 MHz
–160
dBc/Hz
ODC
Output duty cycle
(1)
Not PLL bypass output
45
55
%
(1)
Parameter is specified by characterization and is not tested in production.
(2)
An output frequency over the f
OUT
max spec is possible, but the output swing may be less than the V
OD
min spec.
7.13 AC-CML Output Characteristics (OUTx_P/N)
VDD = 3.3 V ± 5%, VDDO = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5%, T
A
= –40ºC to 85ºC, Output pair AC-coupled to 100-
Ω
differential load, Fast slew rate
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
f
OUT
Output frequency
(1) (2)
750
MHz
V
OD
Output voltage swing (V
OH
-
V
OL
)
f
OUT
≥
25 MHz
400
600
800
mV
V
ODpp
Differential output voltage
swing, peak-to-peak
2 x |V
OD
|
V
V
OS
Output common mode
150
550
mV
t
SKEW
Output-to-output skew
(1)
Same post divider, output divide values, and
output type
100
ps
t
R
/t
F
Output rise/fall time
(1)
20% to 80%, < 300 MHz
150
300
ps
±100 mV around center point, > 300 MHz
200
PN-Floor
Output phase noise floor
(f
OFFSET
= 10 MHz)
156.25 MHz
–160
dBc/Hz
ODC
Output duty cycle
(1)
Not PLL bypass output
45
55
%
Summary of Contents for LMK05028
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