ADV
ANCEINFORMA
TION
Power-on Internal Reset
Pulse or PDN Pin
Sample HW_SW_CTRL
1
0
Hard pin programming mode
I2C is still enabled, LSB of I2C
address is 00
Sample GPIO[4:0] for selecting 1 of 32
pre-defined ROM settings. GPIO[6:5]
are repurposed as devide status
outputs
Soft pin programming mode
I2C Enabled. LSB of I2C address is set
by GPIO[2:1]. GPIO[0] is repurposed as
SYNCN pin for output synchronization.
User can operate from EEPROM loaded configurations or
reprogram the device register via I2C
Save desired configuration
into the EEPROM page
GPIO[4:0] are 2-state
GPIO[6:5] and GPIO[2:0] are
2-state; GPIO[4:3] are 3-state
GPIO[4:3] provides frequency increment/decrement for
DPLL1 and GPIO[6:5] can be programmed as STATUS
outputs or set as frequency increment/decrement for
DPLL2.
Soft pin programming mode
SPI Enabled. GPIO[1] is repurposed as SCS.
GPIO[2] is repurposed as SDO for data
read and GPIO[0] is repurposed as SYNCN
pin for output synchronization.
Float
GPIO[6:5] and GPIO[2:0] are
2-state; GPIO[4:3] are 3-state
39
SNAS724 – FEBRUARY 2018
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Copyright © 2018, Texas Instruments Incorporated
Programming (continued)
•
The serial interface (I2C or SPI) used for register access.
•
The logic pin functionality for control and status.
The I2C or SPI interface allows register access to configure the device after start-up and monitors its status. The
register map configurations are the same for I2C and SPI.
shows the device start-up mode configurations.
shows the logic pin functions used to enter
and operate in each device mode.
Figure 36. LMK05028 Programming Flow
9.5.1 Interface and Control
The system host (MCU, FPGA,) can use either I2C or SPI to access the register, SRAM, and EEPROM maps.
The register and EEPROM map configurations are the same for I2C and SPI. The LMK05028 device blocks can
be initially configured, controlled, and monitored through registers during normal operation (not when the PDN is
low). The host can also control and monitor certain device parameters directly through the external logic control
and status pins.
In the absence of a host, the LMK05028 can self-start from its on-chip EEPROM or ROM page depending on the
state of HW_SW_CTRL pin. The EEPROM or ROM page is used to initialize the registers upon device POR. The
EEPROM can be programmed and read-back through the register interface using I2C or SPI. The contents of
ROM are fixed in hardware and cannot be modified.
Within the device registers, there are certain bits that have read or write access. Other bits are read-only (an
attempt to write to a read-only bit will not change the state of the bit). Certain device registers and bits are
reserved and should not be modified to avoid potential mis-operation of the device.
shows the interface
and control blocks within LMK05028 and the arrows refer to read and write access for the different embedded
memories (SRAM, EEPROM, and ROM).
Summary of Contents for LMK05028
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