ADV
ANCEINFORMA
TION
STATUS0
STATUS1
PDN
HW_SW_CTRL
SCL
SDA
7
6
5
4
3
2
1
0
Reg 0
7
6
5
4
3
2
1
0
Reg1
7
6
5
4
3
2
1
0
Reg2
7
6
5
4
3
2
1
0
Reg3
7
6
5
4
3
2
1
0
Reg28
7
6
5
4
3
2
1
0
Reg29
7
6
5
4
3
2
1
0
Reg199
7
6
5
4
3
2
1
0
Reg200
Device Registers
Device
Hardware
I
2
C/SPI
Port
Control/
Status Pins
Device
Control
And
Status
GPIO4
GPIO3
GPIO2
GPIO1
GPIO0
EEPROM (soft pin mode)
ROM (hard pin mode)
1 of 32 images
SRAM (soft pin mode)
7
6
5
4
3
2
1
0
Reg 0
7
6
5
4
3
2
1
0
Reg1
7
6
5
4
3
2
1
0
Reg2
7
6
5
4
3
2
1
0
Reg3
7
6
5
4
3
2
1
0
Reg86
7
6
5
4
3
2
1
0
Reg87
7
6
5
4
3
2
1
0
Reg88
7
6
5
4
3
2
1
0
Reg89
7
6
5
4
3
2
1
0
Reg 0
7
6
5
4
3
2
1
0
Reg1
7
6
5
4
3
2
1
0
Reg2
7
6
5
4
3
2
1
0
Reg3
7
6
5
4
3
2
1
0
Reg86
7
6
5
4
3
2
1
0
Reg87
7
6
5
4
3
2
1
0
Reg88
7
6
5
4
3
2
1
0
Reg89
7
6
5
4
3
2
1
0
Reg 0
7
6
5
4
3
2
1
0
Reg1
7
6
5
4
3
2
1
0
Reg2
7
6
5
4
3
2
1
0
Reg3
7
6
5
4
3
2
1
0
Reg86
7
6
5
4
3
2
1
0
Reg87
7
6
5
4
3
2
1
0
Reg88
7
6
5
4
3
2
1
0
Reg89
7
6
5
4
3
2
1
0
Reg 0
7
6
5
4
3
2
1
0
Reg1
7
6
5
4
3
2
1
0
Reg2
7
6
5
4
3
2
1
0
Reg3
7
6
5
4
3
2
1
0
Reg86
7
6
5
4
3
2
1
0
Reg87
7
6
5
4
3
2
1
0
Reg88
7
6
5
4
3
2
1
0
Reg89
7
6
5
4
3
2
1
0
Reg 0
7
6
5
4
3
2
1
0
Reg1
7
6
5
4
3
2
1
0
Reg2
7
6
5
4
3
2
1
0
Reg3
7
6
5
4
3
2
1
0
Reg86
7
6
5
4
3
2
1
0
Reg87
7
6
5
4
3
2
1
0
Reg88
7
6
5
4
3
2
1
0
Reg89
7
6
5
4
3
2
1
0
Reg 0
7
6
5
4
3
2
1
0
Reg1
7
6
5
4
3
2
1
0
Reg2
7
6
5
4
3
2
1
0
Reg3
7
6
5
4
3
2
1
0
Reg86
7
6
5
4
3
2
1
0
Reg87
7
6
5
4
3
2
1
0
Reg88
7
6
5
4
3
2
1
0
Reg89
7
6
5
4
3
2
1
0
Reg 0
7
6
5
4
3
2
1
0
Reg1
7
6
5
4
3
2
1
0
Reg2
7
6
5
4
3
2
1
0
Reg3
7
6
5
4
3
2
1
0
Reg86
7
6
5
4
3
2
1
0
Reg87
7
6
5
4
3
2
1
0
Reg88
7
6
5
4
3
2
1
0
Reg89
7
6
5
4
3
2
1
0
Reg 0
7
6
5
4
3
2
1
0
Reg1
7
6
5
4
3
2
1
0
Reg2
7
6
5
4
3
2
1
0
Reg3
7
6
5
4
3
2
1
0
Reg86
7
6
5
4
3
2
1
0
Reg87
7
6
5
4
3
2
1
0
Reg88
7
6
5
4
3
2
1
0
Reg89
7
6
5
4
3
2
1
0
Reg 0
7
6
5
4
3
2
1
0
Reg1
7
6
5
4
3
2
1
0
Reg2
7
6
5
4
3
2
1
0
Reg3
7
6
5
4
3
2
1
0
Reg86
7
6
5
4
3
2
1
0
Reg87
7
6
5
4
3
2
1
0
Reg88
7
6
5
4
3
2
1
0
Reg89
7
6
5
4
3
2
1
0
Reg 0
7
6
5
4
3
2
1
0
Reg1
7
6
5
4
3
2
1
0
Reg2
7
6
5
4
3
2
1
0
Reg3
7
6
5
4
3
2
1
0
Reg86
7
6
5
4
3
2
1
0
Reg87
7
6
5
4
3
2
1
0
Reg88
7
6
5
4
3
2
1
0
Reg89
7
6
5
4
3
2
1
0
Reg 0
7
6
5
4
3
2
1
0
Reg1
7
6
5
4
3
2
1
0
Reg2
7
6
5
4
3
2
1
0
Reg3
7
6
5
4
3
2
1
0
Reg86
7
6
5
4
3
2
1
0
Reg87
7
6
5
4
3
2
1
0
Reg88
7
6
5
4
3
2
1
0
Reg89
7
6
5
4
3
2
1
0
Reg 0
7
6
5
4
3
2
1
0
Reg1
7
6
5
4
3
2
1
0
Reg2
7
6
5
4
3
2
1
0
Reg3
7
6
5
4
3
2
1
0
Reg86
7
6
5
4
3
2
1
0
Reg87
7
6
5
4
3
2
1
0
Reg88
7
6
5
4
3
2
1
0
Reg89
7
6
5
4
3
2
1
0
Reg 0
7
6
5
4
3
2
1
0
Reg1
7
6
5
4
3
2
1
0
Reg2
7
6
5
4
3
2
1
0
Reg3
7
6
5
4
3
2
1
0
Reg86
7
6
5
4
3
2
1
0
Reg87
7
6
5
4
3
2
1
0
Reg88
7
6
5
4
3
2
1
0
Reg89
7
6
5
4
3
2
1
0
Reg 0
7
6
5
4
3
2
1
0
Reg1
7
6
5
4
3
2
1
0
Reg2
7
6
5
4
3
2
1
0
Reg3
7
6
5
4
3
2
1
0
Reg86
7
6
5
4
3
2
1
0
Reg87
7
6
5
4
3
2
1
0
Reg88
7
6
5
4
3
2
1
0
Reg89
7
6
5
4
3
2
1
0
Reg 0
7
6
5
4
3
2
1
0
Reg1
7
6
5
4
3
2
1
0
Reg2
7
6
5
4
3
2
1
0
Reg3
7
6
5
4
3
2
1
0
Reg86
7
6
5
4
3
2
1
0
Reg87
7
6
5
4
3
2
1
0
Reg88
7
6
5
4
3
2
1
0
Reg89
7
6
5
4
3
2
1
0
Reg 0
7
6
5
4
3
2
1
0
Reg1
7
6
5
4
3
2
1
0
Reg2
7
6
5
4
3
2
1
0
Reg3
7
6
5
4
3
2
1
0
Reg86
7
6
5
4
3
2
1
0
Reg87
7
6
5
4
3
2
1
0
Reg88
7
6
5
4
3
2
1
0
Reg89
GPIO6
GPIO5
7
6
5
4
3
2
1
0
Reg 0
7
6
5
4
3
2
1
0
Reg1
7
6
5
4
3
2
1
0
Reg2
7
6
5
4
3
2
1
0
Reg3
7
6
5
4
3
2
1
0
Reg28
7
6
5
4
3
2
1
0
Reg29
7
6
5
4
3
2
1
0
Reg199
7
6
5
4
3
2
1
0
Reg200
7
6
5
4
3
2
1
0
Reg 0
7
6
5
4
3
2
1
0
Reg1
7
6
5
4
3
2
1
0
Reg2
7
6
5
4
3
2
1
0
Reg3
7
6
5
4
3
2
1
0
Reg28
7
6
5
4
3
2
1
0
Reg29
7
6
5
4
3
2
1
0
Reg199
7
6
5
4
3
2
1
0
Reg200
40
SNAS724 – FEBRUARY 2018
Product Folder Links:
Copyright © 2018, Texas Instruments Incorporated
Programming (continued)
NOTE: The internal ROM has 16 pages selectable by GPIO[3:0] pins in Hard pin mode (not 32 pages as shown).
Figure 37. Device Control, Register, and Memory Interfaces
Summary of Contents for LMK05028
Page 57: ......