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ADV
ANCEINFORMA
TION
100
SWLVDS
SWHCSL
50
SWHCSL
50
SWAC
SWAC
7pF
7pF
Differential Input Control
IN_P/
XO_P/
TCXO_P
IN_N/XO_N
LMK05028
Copyright © 2018, Texas Instruments Incorporated
22
SNAS724 – FEBRUARY 2018
Product Folder Links:
Copyright © 2018, Texas Instruments Incorporated
Feature Description (continued)
9.3.2 TCXO Input (TCXO_IN)
The TCXO input is the reference clock to the TCXO-DPLL loop in each PLL core. When the PLL core uses the
TCXO-DPLL in 3-loop mode (typically), the TCXO input determines the wander and close-in phase noise
performance when the DPLL is locked, and the frequency accuracy and stability during holdover mode. A TCXO
input with high phase noise floor should have minimal or no impact on the output jitter performance, provided the
TCXO loop bandwidth is designed low enough to attenuate its noise contribution. When the TCXO input is not
used, the XO determines the frequency accuracy and stability during free-run or holdover modes.
The TCXO input accepts an AC-coupled single-ended clock (sine, clipped-sine, or square wave) and has a
internal weak bias of about 0.6 V. The input voltage swing should be less than 1.2 Vpp and attenuated or
terminated before AC-coupling to the pin. This input can be driven from a low-frequency TCXO, OCXO, or
external timing reference that conforms to the frequency accuracy and holdover stability requirements required
by the application. TCXO and OCXO frequencies of 10 to 12.8 MHz are widely available and cost-effective
options.
9.3.3 Reference Inputs (INx_P/N)
The reference inputs (IN0 to IN3) can accept differential or LVCMOS clocks to lock either or both DPLLs. Each
DPLL has an input mux to select one of the four inputs. Each DPLL can support switching between two or more
inputs with different frequencies provided each input can be divided down by DPLL reference dividers
(DPLLy_REFx_RDIV) to a single common frequency.
Each input has programmable input type, on-chip termination, and biasing controls to support any clock interface
type.
shows the input termination and biasing options implemented on the reference and XO inputs. The
internal switch options are register configurable.
shows the typical input buffer configurations to interface
with LVDS, CML, LVPECL HCSL, and LVCMOS drivers.
Figure 19. Input Buffer Termination Options for Reference, XO, and TCXO Inputs
Summary of Contents for LMK05028
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