Texas Instruments Delfino TMS320F28374S, Manual

Page: 97 / 198

ADV
ANCEINFORMA
TION
TMS320F28377S, TMS320F28376S, TMS320F28375S, TMS320F28374S
www.ti.com SPRS881A – AUGUST 2014 – REVISED JUNE 2015
Table 5-42. ADC Operating Conditions (12-Bit Single-Ended Mode)
over recommended operating conditions (unless otherwise noted)
MIN TYP MAX UNIT
Input clock 5 50 MHz
75 ns
Sample window duration
1 ADCCLK
Conversion range V
REFLO
V
REFHI
V
V
REFHI
2.4 2.5 or 3.0 V
DDA
V
V
REFLO
V
SSA
0 V
SSA
V
Table 5-43. ADC Characteristics (12-Bit Single-Ended Mode)
over recommended operating conditions (unless otherwise noted)
(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ADC conversion cycles
(2)
10.1 11 ADCCLKs
Power-up time 500 µs
Gain error –8 ±6 8 LSBs
Offset error –4 ±2 4 LSBs
Channel-to-channel gain error ±4 LSBs
Channel-to-channel offset error ±2 LSBs
ADC-to-ADC gain error Identical V
REFHI
and V
REFLO
for all ADCs TBD LSBs
ADC-to-ADC offset error Identical V
REFHI
and V
REFLO
for all ADCs TBD LSBs
DNL
(3)
> –1 ±0.5 1 LSBs
INL –2 ±1.0 2 LSBs
SNR V
REFHI
= 2.5 V, f
in
= 100 kHz
(4)
67.8 dB
THD V
REFHI
= 2.5 V, f
in
= 100 kHz
(4)
–78.4 dB
SFDR V
REFHI
= 2.5 V, f
in
= 100 kHz
(4)
79.2 dB
SINAD V
REFHI
= 2.5 V, f
in
= 100 kHz
(4)
67.7 dB
ENOB V
REFHI
= 2.5 V, f
in
= 100 kHz
(4)
11.0 bits
V
DDA
= 3.3-V DC + 200 mV
PSRR 60 dB
Sine at 1 kHz
V
DDA
= 3.3-V DC + 200 mV
PSRR 57 dB
Sine at 800 kHz
ADC-to-ADC isolation
±1 LSBs
(synchronous)
(5) (6)
ADC-to-ADC isolation
TBD LSBs
(asynchronous)
(5) (7)
(1) Typical values are measured with V
REFHI
= 2.5 V and V
REFLO
= 0 V. Minimum and Maximum values are tested or characterized with
V
REFHI
= 2.5 V and V
REFLO
= 0 V.
(2) See Section 5.8.1.1.2 .
(3) No missing codes.
(4) AC parameters will be impacted by clock source accuracy and jitter, this should be taken into account when selecting the clock source
for the system. The clock source used for these parameters was a high-accuracy external clock fed through the PLL. The on-chip
Internal Oscillator has higher jitter than an external crystal and these parameters will degrade if it is used as a clock source.
(5) Code deviation due to operation of multiple ADCs simultaneously.
(6) All ADCs operating with identical ADCCLK, S+H duration, and triggers.
(7) All ADCs operating with heterogenous ADCCLK, S+H duration, or triggers.
Copyright © 2014–2015, Texas Instruments Incorporated
Specifications 97
Submit Documentation Feedback
Product Folder Links: TMS320F28377S TMS320F28376S TMS320F28375S TMS320F28374S