Texas Instruments Delfino TMS320F28374S Manual Download Page 164

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ADV

ANCEINFORMA

TION

CLK

START

ENABLE

DATA[n:0]

WAIT

Data2

Data1

Data3

Data4

Data5

Data6

Data7

Data8

Data9

CLK

START

ENABLE

DATA[n:0]

WAIT

TMS320F28377S, TMS320F28376S, TMS320F28375S, TMS320F28374S

SPRS881A – AUGUST 2014 – REVISED JUNE 2015

www.ti.com

Figure 5-71. uPP Single Data Rate (SDR) Transmit Timing

Figure 5-72. uPP Double Data Rate (DDR) Transmit Timing

164

Specifications

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Summary of Contents for Delfino TMS320F28374S

Page 1: ...Core 3 3 V I O Design Digital to Analog Converter DAC References System Peripherals Three 12 Bit Buffered DAC Outputs Two External Memory Interfaces EMIFs With Enhanced Control Peripherals ASRAM and...

Page 2: ...hermally Enhanced Low Q100 Qualification for Automotive Applications Profile Quad Flatpack HLQFP PTP Suffix 100 Pin PowerPAD Thermally Enhanced Thin Quad Flatpack HTQFP PZP Suffix 1 2 Applications Ind...

Page 3: ...analog signals which ultimately boosts system throughput New sigma delta peripherals enable isolated current shunt measurements and windowed comparators allow protection of power stage when current l...

Page 4: ...CLA1 to CPU1 128x16 MSG RAM CPU1 to CPU1 CLA1 128x16 MSG RAM Boot ROM 32Kx16 Non Secure Secure ROM 32Kx16 Secure CPU1 M0 RAM 1Kx16 CPU1 M1 RAM 1Kx16 CPU1 D0 RAM 2Kx16 CPU1 D1 RAM 2Kx16 CPU1 Local Shar...

Page 5: ...escriptions 18 7 Device and Documentation Support 185 4 3 Pins With Internal Pullup and Pulldown 41 7 1 Device Support 185 4 4 Pin Multiplexing 42 7 2 Documentation Support 188 5 Specifications 50 7 3...

Page 6: ...ternal clock input to Crystal oscillator External clock input 10 Table 3 1 Updated SDFM channels for 100 Pin PZP package 10 Table 3 1 Updated temperature ranges see Global changes 10 Table 3 1 Removed...

Page 7: ...eset footnote 63 Figure 5 6 Connecting Input Clocks to a 2837xS Device Updated figure 64 Section 5 7 3 4 Crystal Oscillator Added section 65 Table 5 14 Crystal Oscillator Parameters Added table 65 Tab...

Page 8: ...dule Updated The SDFM is a four channel digital filter paragraph 121 Section 5 9 5 Removed Ability to bypass filter module feature 121 Figure 5 43 SDFM Updated figure 122 Section 5 9 5 1 SDFM Electric...

Page 9: ...heral Access Updated These modules are on a Peripheral Frame with DMA access footnote 173 Figure 6 3 DMA Block Diagram Updated figure 178 Section 6 6 4 Boot ROM and Peripheral Booting Added NOTE about...

Page 10: ...Boot ROM Yes One Time Programmable OTP memory 2KW 16 bit words System 32 bit CPU timers 3 Watchdog timers 1 Nonmaskable Interrupt Watchdog NMIWD 1 timers Crystal oscillator External clock input 1 0 p...

Page 11: ...ion S 40 C to 125 C Yes Temperature TJ Yes No Q 40 C to 150 C 5 Free Air Temperature Yes No Q 40 C to 125 C 5 TA 1 A type change represents a major functional feature difference in a peripheral module...

Page 12: ...9 8 7 TMS320F28377S TMS320F28376S TMS320F28375S TMS320F28374S SPRS881A AUGUST 2014 REVISED JUNE 2015 www ti com 4 Terminal Configuration and Functions 4 1 Pin Diagrams Figure 4 1 to Figure 4 4 show t...

Page 13: ...T R P N M L K GPIO45 GPIO44 GPIO142 GPIO140 GPIO141 GPIO57 GPIO139 GPIO55 GPIO54 GPIO50 GPIO137 GPIO135 GPIO134 GPIO132 GPIO51 GPIO138 ERRORSTS VDDIO VSS 12 11 M L K N M L K 13 12 11 TMS320F28377S TM...

Page 14: ...S VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD VDD VDD VDD VDD VDD VDDIO VDDOSC VDDOSC VDDIO VDDIO VDDIO VDDIO VSSOSC VSSOSC H J 12 11 13 12 11 H G J TMS320F28377S TMS320F28376S TMS320F28375S TMS32...

Page 15: ...VSS VSS VSS VSS 10 9 8 J H J H G 10 9 8 F E D C B GPIO157 GPIO160 GPIO163 GPIO164 GPIO0 GPIO1 GPIO161 GPIO162 GPIO158 GPIO159 A VDD VDD VSS VSS VSS VDDIO VDDIO VDDIO 10 9 8 7 TMS320F28377S TMS320F283...

Page 16: ...GPIO50 GPIO49 GPIO48 GPIO41 ERRORSTS VREGENZ X1 X2 XRS GPIO43 GPIO42 GPIO47 GPIO46 V SSOSC V DD V DD V DDIO V DDOSC V DDOSC V DDIO V DDIO V DDIO V DDIO V DDIO GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO1...

Page 17: ...O41 GPIO58 GPIO59 GPIO60 GPIO61 GPIO62 GPIO63 GPIO64 GPIO65 GPIO66 VREGENZ X1 X2 GPIO43 GPIO42 XRS V DDIO V DDOSC V DDIO V DDIO V DDOSC V DD V DD V SSOSC V DDIO V DDIO V DDIO V DD V V SSA REFLOA V DDA...

Page 18: ...e placed as close to the device as possible between the VREFHIC and VREFLOC pins ADC D high reference Place at least a 1 F capacitor on this pin for the 12 bit mode or at least a 22 F VREFHID V5 55 I...

Page 19: ...DACs place at least a 1 F capacitor on this pin ADCINB1 I ADC B input 1 There is a 50 k internal pulldown on this pin in both an ADC input or DAC output mode which W2 47 29 cannot be disabled DACOUTC...

Page 20: ...PIO4 0 4 8 12 I O General purpose input output 4 EPWM3A 1 O Enhanced PWM3 output A and HRPWM channel C7 164 93 OUTPUTXBAR3 5 O Output 3 of the output XBAR CANTXA 6 O CAN A transmit GPIO5 0 4 8 12 I O...

Page 21: ...BAR EQEP1B 5 I Enhanced QEP1 input B UPP STRT 15 I O Universal parallel port start Transmitter asserts at start of DMA line GPIO12 0 4 8 12 I O General purpose input output 12 EPWM7A 1 O Enhanced PWM7...

Page 22: ...AR EPWM9B 5 O Enhanced PWM9 output B SD1_C1 7 I Sigma Delta 1 channel 1 clock input UPP D3 15 I O Universal parallel port data line 3 GPIO18 0 4 8 12 I O General purpose input output 18 SPICLKA 1 I O...

Page 23: ...SCI B receive data EPWM12B 5 O Enhanced PWM12 output B SPISTEB 6 I O SPI B slave transmit enable SD1_C4 7 I Sigma Delta 1 channel 4 clock input GPIO24 0 4 8 12 I O General purpose input output 24 OUT...

Page 24: ...e EM1CLK 2 O External memory interface 1 clock T11 63 OUTPUTXBAR7 5 O Output 7 of the output XBAR EQEP3S 6 I O Enhanced QEP3 strobe SD2_D4 7 I Sigma Delta 2 channel 4 data input GPIO31 0 4 8 12 I O Ge...

Page 25: ...this pin serves as the GPIOHIBWAKE signal For details see the Low Power Modes section of the System Control chapter in the U17 89 51 TMS320F2837xS Delfino Microcontrollers Technical Reference Manual...

Page 26: ...nnel 2 clock input GPIO52 0 4 8 12 I O General purpose input output 52 EQEP1S 1 I O Enhanced QEP1 strobe EM1A12 2 P16 96 O External memory interface 1 address line 12 SPICLKC 6 I O SPI C clock SD1_D3...

Page 27: ...face 1 data line 26 EM2D10 3 I O External memory interface 2 data line 10 N17 103 52 OUTPUTXBAR1 5 O Output 1 of the output XBAR SPICLKB 6 I O SPI B clock SD2_D2 7 I Sigma Delta 2 channel 2 data input...

Page 28: ...109 58 EQEP3B 5 I Enhanced QEP3 input B CANTXA 6 O CAN A transmit SD2_C4 7 I Sigma Delta 2 channel 4 clock input SPISIMOB 15 I O SPI B slave in master out 3 GPIO64 0 4 8 12 I O General purpose input o...

Page 29: ...B transmit SCITXDC 6 O SCI C transmit data SPISTEC 15 I O SPI C slave transmit enable 3 GPIO73 0 4 8 12 I O General purpose input output 73 EM1D11 2 I O External memory interface 1 data line 11 XCLKOU...

Page 30: ...eceive serial data MDRA 15 I McBSP A receive serial data GPIO86 0 4 8 12 I O General purpose input output 86 EM1A13 2 O External memory interface 1 address line 13 EM1CAS 3 O External memory interface...

Page 31: ...0 2 4 8 I O General purpose input output 97 EM2DQM0 3 A2 O External memory interface 2 Input output mask for byte 0 EQEP1B 5 I Enhanced QEP1 input B GPIO98 0 2 4 8 I O General purpose input output 98...

Page 32: ...4 8 12 I O General purpose input output 110 M2 EM2WAIT 3 I External memory interface 2 Asynchronous SRAM WAIT GPIO111 0 4 8 12 I O General purpose input output 111 M4 EM2BA0 3 O External memory interf...

Page 33: ...ut output 128 W9 SD1_D4 7 I Sigma Delta 1 channel 4 data input GPIO129 0 4 8 12 I O General purpose input output 129 T10 SD1_C4 7 I Sigma Delta 1 channel 4 clock input GPIO130 0 4 8 12 I O General pur...

Page 34: ...General purpose input output 148 D14 EPWM2B 1 O Enhanced PWM2 output B and HRPWM channel GPIO149 0 4 8 12 I O General purpose input output 149 A13 EPWM3A 1 O Enhanced PWM3 output A and HRPWM channel...

Page 35: ...4 8 12 I O General purpose input output 163 A8 EPWM10A 1 O Enhanced PWM10 output A GPIO164 0 4 8 12 I O General purpose input output 164 B8 EPWM10B 1 O Enhanced PWM10 output B GPIO165 0 4 8 12 I O Ge...

Page 36: ...On chip crystal oscillator output A quartz crystal may be X2 J19 121 66 O connected across X1 and X2 If X2 is not used it must be left unconnected NO CONNECT No connect BGA ball is electrically open...

Page 37: ...26 78 1 2 V digital logic power pins TI recommends placing a decoupling capacitor near each VDD pin with a minimum J14 137 84 VDD total capacitance of approximately 20 uF The exact J15 153 89 value of...

Page 38: ...G5 114 3 3 V digital I O power pins Place a minimum 0 1 F VDDIO decoupling capacitor on each pin G6 116 H5 127 H6 138 L14 147 L15 152 M1 159 M5 168 M6 N14 N15 P9 R9 V19 W8 H16 120 65 Power pins for t...

Page 39: ...5 F5 F6 F8 F12 F14 F15 G16 G17 H8 H9 H10 Analog and digital ground For Quad Flatpacks QFPs H11 PWR PWR VSS the PowerPAD on the bottom of the package must be PAD PAD H12 soldered to the ground plane of...

Page 40: ...R7 R8 R14 R15 W7 W19 H18 122 67 Crystal oscillator X1 and X2 ground pin When using an external crystal do not connect this pin to the board ground Instead connect it to the ground reference of the VSS...

Page 41: ...m level signal integrity analysis be performed with the provided IBIS models The termination is not required if this pin is used for input function 4 3 Pins With Internal Pullup and Pulldown Some pins...

Page 42: ...KXB I O OUTPUTXBAR3 O UPP D6 I O GPIO15 EPWM8B O SCIRXDB I MFSXB I O OUTPUTXBAR4 O UPP D5 I O GPIO16 SPISIMOA I O CANTXB O OUTPUTXBAR7 O EPWM9A O SD1_D1 I UPP D4 I O GPIO17 SPISOMIA I O CANRXB I OUTPU...

Page 43: ...OUTPUTXBAR4 O SPISOMIB I O SD2_C3 I SPISTEA 3 I O GPIO62 SCIRXDC I EM1D22 I O EM2D6 I O EQEP3A I CANRXA I SD2_D4 I GPIO63 SCITXDC O EM1D21 I O EM2D5 I O EQEP3B I CANTXA O SD2_C4 I SPISIMOB 3 I O GPIO...

Page 44: ...LA I OD EM2A7 O EQEP3B I SCIRXDD I GPIO106 EM2A8 O EQEP3S I O SCITXDC O GPIO107 EM2A9 O EQEP3I I O SCIRXDC I GPIO108 EM2A10 O GPIO109 EM2A11 O GPIO110 EM2WAIT I GPIO111 EM2BA0 O GPIO112 EM2BA1 O GPIO1...

Page 45: ...EPWM1B O GPIO147 EPWM2A O GPIO148 EPWM2B O GPIO149 EPWM3A O GPIO150 EPWM3B O GPIO151 EPWM4A O GPIO152 EPWM4B O GPIO153 EPWM5A O GPIO154 EPWM5B O GPIO155 EPWM6A O GPIO156 EPWM6B O GPIO157 EPWM7A O GPIO...

Page 46: ...ernal interrupts XINT For details on configuring the Input X BAR see the General Purpose Input Output GPIO chapter of the TMS320F2837xS Delfino Microcontrollers Technical Reference Manual SPRUHX5 Figu...

Page 47: ...PUT3 OUTPUT4 OUTPUT5 OUTPUT6 OUTPUT7 OUTPUT8 TMS320F28377S TMS320F28376S TMS320F28375S TMS320F28374S www ti com SPRS881A AUGUST 2014 REVISED JUNE 2015 4 4 3 Output X BAR The Output X BAR has eight out...

Page 48: ...OUTL ADCBEVT3 13 CMPSS7 CTRIPOUTL ADCSOCA ADCDEVT3 14 CMPSS8 CTRIPOUTH CMPSS8 CTRIPOUTH_OR_CTRIPOUTL ADCBEVT4 EXTSYNCOUT 15 CMPSS8 CTRIPOUTL ADCSOCB ADCDEVT4 16 SD1FLT1 COMPH SD1FLT1 COMPH_OR_COMPL 17...

Page 49: ...58 SPISIMOA GPBGMUX2 21 20 11b GPBMUX2 21 20 11b GPIO59 SPISOMIA GPBGMUX2 23 22 11b GPBMUX2 23 22 11b GPIO60 SPICLKA GPBGMUX2 25 24 11b GPBMUX2 25 24 11b GPIO61 SPISTEA GPBGMUX2 27 26 11b GPBMUX2 27 2...

Page 50: ...s not implied Exposure to absolute maximum rated conditions for extended periods may affect device reliability 2 All voltage values are with respect to VSS unless otherwise noted 3 Long term high temp...

Page 51: ...TYP MAX UNIT CONDITIONS IOH IOH MIN VDDIO 0 8 VOH High level output voltage V IOH 100 A VDDIO 0 2 IOL IOL MAX 0 4 VOL Low level output voltage V IOL 100 A 0 2 IOH High level output source current for...

Page 52: ...powered down XCLKOUT is turned off CPU1 M0 and CPU1 M1 RAMs are in HIBERNATE 100 A 4 mA 750 A 1 mA 5 A 75 A 1 A 50 A low power data retention mode CPU1 is running from RAM All I O pins are left uncon...

Page 53: ...ent Consumption Graphs The following graphs are a typical representation of the relationship between frequency and current consumption power on the device The Operational test from Table 5 1 was run a...

Page 54: ...ency Power Power W SYSCLK MHz TMS320F28377S TMS320F28376S TMS320F28375S TMS320F28374S SPRS881A AUGUST 2014 REVISED JUNE 2015 www ti com Figure 5 2 Power Versus Frequency 54 Specifications Copyright 20...

Page 55: ...indicates the typical current reduction that may be achieved by disabling the clocks using the PCLKCRx register Table 5 2 Typical Current Consumption by Various Peripherals at 200 MHz 1 PERIPHERAL ID...

Page 56: ...Boards for Area Array Surface Mount Package Thermal Measurements 2 lfm linear feet per minute 5 6 2 PTP Package C W 1 AIR FLOW lfm 2 R JC Junction to case thermal resistance 6 97 N A R JB Junction to...

Page 57: ...tem with the exception of the Theta JC R JC value which is based on a JEDEC defined 1S0P system and will change based on environment as well as application For more information see these EIA JEDEC sta...

Page 58: ...circuit may also drive this pin to assert a device reset This pin is also driven low by the MCU when a watchdog reset occurs During watchdog reset the XRS pin is driven low for the watchdog reset dura...

Page 59: ...in low until the supplies are in a valid range B After reset the boot ROM code samples Boot Mode pins Based on the status of the Boot Mode pin the boot code branches to destination memory or boot code...

Page 60: ...k for External crystal connected between X1 and X2 pins On chip crystal oscillator enables the use of external crystal resonator to provide Main PLL time base when connected to the device Auxiliary PL...

Page 61: ...CLKDIVSEL INTOSC1 INTOSC2 XTAL AUXCLKIN AUXCLK Divider AUXCLKDIVSEL CAN Bit Clock CLKSRCCTL2 To CANs One per CAN module To ePIEs LS RAMs CLA message RAMs and DCSMs To local memories SYSCLK PERx LSPCLK...

Page 62: ...evel Characteristics When Using an External Clock Source Not a Crystal over recommended operating conditions unless otherwise noted PARAMETER MIN MAX UNIT X1 VIL Valid low level input voltage 0 3 0 3...

Page 63: ...MHz 1 Lower LSPCLK will reduce device power consumption The default at reset is SYSCLK 4 2 For SYSCLK above 100 MHz the EPWMCLK must be half of SYSCLK 5 7 3 2 3 Output Clock Frequency and Switching C...

Page 64: ...ti com 5 7 3 3 Input Clocks and PLLs In addition to the internal 0 pin oscillators multiple external clock source options are available Figure 5 6 shows the recommended methods of connecting crystals...

Page 65: ...ters MIN MAX UNIT CL1 CL2 Load capacitance 12 24 pF C0 Crystal shunt capacitance 7 pF Table 5 15 Crystal Equivalent Series Resistance ESR Requirements 1 MAXIMUM ESR MAXIMUM ESR CRYSTAL FREQUENCY MHz C...

Page 66: ...d to frequencies above 194 MHz Table 5 17 Internal Oscillator Electrical Characteristics over recommended operating conditions unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Nominal...

Page 67: ...to RAM Code that uses Flash API to program the Flash Flash API itself Flash data to be programmed In other words the time indicated in this table is applicable after all the required code data is avai...

Page 68: ...D Power Detect terminal of the emulator header should be connected to the board 3 3 V supply Header GND terminals should be connected to board ground TDIS Cable Disconnect Sense should also be connect...

Page 69: ...F28374S www ti com SPRS881A AUGUST 2014 REVISED JUNE 2015 Figure 5 8 Connecting to the 20 Pin JTAG Header 5 7 6 GPIO Electrical Data and Timing 5 7 6 1 GPIO Output Timing Table 5 22 General Purpose Ou...

Page 70: ...nal A This glitch will be ignored by the input qualifier The QUALPRD bit field specifies the qualification sampling period It can vary from 00 to 0xFF If QUALPRD 00 then the sampling period is 1 SYSCL...

Page 71: ...ates the time period of SYSCLK Sampling period SYSCLK cycle if QUALPRD 0 In a given sampling window either 3 or 6 samples of the input signal are taken to determine the validity of the signal This is...

Page 72: ...A AUGUST 2014 REVISED JUNE 2015 www ti com 5 7 7 Interrupts Figure 5 12 provides a high level view of the interrupt architecture As shown in Figure 5 12 the devices support five external interrupts XI...

Page 73: ...see Table 5 23 2 This timing is applicable to any GPIO pin configured for ADCSOC functionality Table 5 25 External Interrupt Switching Characteristics 1 over recommended operating conditions unless ot...

Page 74: ...tive Active Gated PLL Powered Powered Powered Down INTOSC1 Powered Powered Powered down if CLKSRCCTL1 WDHALTI 0 INTOSC2 Powered Powered Powered down if CLKSRCCTL1 WDHALTI 0 Flash Powered Powered Softw...

Page 75: ...sume 2 Without input qualifier 40tc SYSCLK Wakeup from Flash Flash module in active state With input qualifier 40tc SYSCLK tw WAKE td WAKE IDLE Without input qualifier 6700tc SYSCLK cycles Wakeup from...

Page 76: ...IDLE instruction executed to td IDLE XCOS 16tc INTOSC1 cycles XCLKOUT stop Delay time external wake signal to program execution resume 1 Without input qualifier 175tc SYSCLK Wakeup from flash Flash m...

Page 77: ...TANDBY mode After the IDLE instruction is executed a delay of five OSCCLK cycles minimum is needed before the wakeup signal could be asserted D The external wakeup signal is driven active E The wakeup...

Page 78: ...cst 8tc OSCCLK cycles Table 5 33 HALT Mode Switching Characteristics over recommended operating conditions unless otherwise noted PARAMETER MIN MAX UNIT td IDLE XCOS Delay time IDLE instruction execut...

Page 79: ...uld be asserted D When the GPIOn pin used to bring the device out of HALT is driven low the oscillator is turned on and the oscillator wakeup sequence is initiated The GPIO pin should be driven high o...

Page 80: ...ation HIBWAKE signal 40 s tw WAKEXRS Pulse duration XRS wakeup signal 40 s Table 5 35 HIBERNATE Mode Switching Characteristics over recommended operating conditions unless otherwise noted PARAMETER MI...

Page 81: ...emainder of the device F The BootROM will then begin to execute The BootROM can distinguish a HIBERNATE wakeup by reading the CPU1 REC HIBRESETn bit After the OTP trims are loaded the BootROM code wil...

Page 82: ...of the program address bus and can only be accessed through the data bus which places a restriction on the C compiler being able to work effectively on data in this space Therefore when using SDRAM t...

Page 83: ...WC 16 E 3 EWC 16 E 2 Output setup time EMxCS y 2 low RS E 3 RS E 2 ns to EMxOE low SS 0 4 tsu EMCEL EMOEL Output setup time EMxCS y 2 low 3 2 ns to EMxOE low SS 1 Output hold time EMxOE high to RH E 3...

Page 84: ...WH E ns EMxCS y 2 high SS 0 17 th EMWEH EMCEH Output hold time EMxWE high to 3 0 ns EMxCS y 2 high SS 1 Output setup time EMxDQM y 0 18 tsu EMDQMV EMWEL WS E 3 WS E 1 ns valid to EMxWE low Output hol...

Page 85: ...10 5 9 7 4 8 6 3 1 EMxDQM y 0 30 29 TMS320F28377S TMS320F28376S TMS320F28375S TMS320F28374S www ti com SPRS881A AUGUST 2014 REVISED JUNE 2015 Figure 5 18 Asynchronous Memory Read Timing Figure 5 19 EM...

Page 86: ...xA y 0 EMxOE EMxD y 0 EMxWE EMxDQM y 0 TMS320F28377S TMS320F28376S TMS320F28375S TMS320F28374S SPRS881A AUGUST 2014 REVISED JUNE 2015 www ti com Figure 5 20 Asynchronous Memory Write Timing Figure 5 2...

Page 87: ...g to EMxDQM y 0 invalid 1 ns 7 td CLKH AV Delay time EMxCLK rising to EMxA y 0 and EMxBA y 0 valid 8 ns 8 toh CLKH AIV Output hold time EMxCLK rising to EMxA y 0 and EMxBA y 0 invalid 1 ns 9 td CLKH D...

Page 88: ...A y 0 EMxD y 0 EMxWE EMxDQM y 0 TMS320F28377S TMS320F28376S TMS320F28375S TMS320F28374S SPRS881A AUGUST 2014 REVISED JUNE 2015 www ti com Figure 5 22 Basic SDRAM Read Operation 88 Specifications Copyr...

Page 89: ...y 0 EMxWE EMxDQM y 0 TMS320F28377S TMS320F28376S TMS320F28375S TMS320F28374S www ti com SPRS881A AUGUST 2014 REVISED JUNE 2015 Figure 5 23 Basic SDRAM Write Operation Copyright 2014 2015 Texas Instru...

Page 90: ...stems each containing two 12 bit reference DACs two comparators and a digital deglitching filter Three 12 bit buffered output DACs Figure 5 24 shows the Analog Subsystem Block Diagram for the 337 ball...

Page 91: ...4L CMPIN5P CMPIN6P CMPIN5N CTRIPOUT5H CTRIP5H CTRIP5L CMPIN6N CTRIPOUT6H CTRIP6H CTRIP6L CTRIPOUT5L CTRIPOUT6L CMPIN7P CMPIN8P CMPIN7N CTRIPOUT7H CTRIP7H CTRIP7L CMPIN8N CTRIPOUT8H CTRIP8H CTRIP8L CTR...

Page 92: ...CTRIPOUT8H CTRIP8H CTRIP8L CTRIPOUT7L CTRIPOUT8L 12 bit Buffered DAC VREFHIA VDAC 12 bit Buffered DAC VREFHIB DACOUTC VDAC REFHI DAC12 DAC12 Comparator Subsystem 2 VDDA or VDAC Digital Filter Digital...

Page 93: ...P3H CTRIP3L CMPIN4N CTRIPOUT4H CTRIP4H CTRIP4L Digital Filter CTRIPOUT1L CTRIPOUT2H CTRIPOUT2L CTRIPOUT3L CTRIPOUT4L 12 bit Buffered DAC VREFHIA VDAC 12 bit Buffered DAC VREFHIB DACOUTC VDAC REFHI DAC...

Page 94: ...etric external reference set by VREFHI and VREFLO Differential signal conversions 16 bit mode only Single ended signal conversions 12 bit mode only Input multiplexer with up to 16 channels single ende...

Page 95: ...LMODE Post Processing Block 1 4 15 0 SIGNALMODE RESOLUTION RESULT ADCRESULT 0 15 Regs ADCPPBxRESULT Event Logic ADCEVTINT 15 0 ADCEVT TRIGGER 15 0 Trigger Timestamp SOC Delay Timestamp ADCCOUNTER ADCP...

Page 96: ...R VREFHI 2 5 V fin 10 kHz 5 95 4 dB SINAD VREFHI 2 5 V fin 10 kHz 5 86 6 dB ENOB VREFHI 2 5 V fin 10 kHz 5 14 1 bits VDDA 3 3 V DC 200 mV PSRR 77 dB Sine at 1 kHz VDDA 3 3 V DC 200 mV PSRR 74 dB Sine...

Page 97: ...79 2 dB SINAD VREFHI 2 5 V fin 100 kHz 4 67 7 dB ENOB VREFHI 2 5 V fin 100 kHz 4 11 0 bits VDDA 3 3 V DC 200 mV PSRR 60 dB Sine at 1 kHz VDDA 3 3 V DC 200 mV PSRR 57 dB Sine at 800 kHz ADC to ADC iso...

Page 98: ...MODE Cp Parasitic input capacitance See Table 5 46 Ron Sampling switch resistance 425 Ch Sampling capacitor 14 5 pF Rs Nominal source impedance 50 Figure 5 28 Single Ended Input Model For differential...

Page 99: ...ADCIN14 8 6 10 0 ADCIN15 9 0 11 5 These input models should be used along with actual signal source impedance to determine the acquisition window duration See the Choosing an Acquisition Window Durati...

Page 100: ...cycles ACQPS can be configured individually for each SOC so tSH will not necessarily be the same for different SOCs The parameter tLAT is the time from the end of the S H window until the ADC convers...

Page 101: ...ADCCTL2 PRESCALE PRESCALE RATIO tEOC tLAT EARLY LATE CYCLES ADCCLKs 0 1 11 12 0 12 11 0 2 2 21 22 0 22 10 5 3 2 5 26 27 0 27 10 4 4 3 31 33 0 33 10 3 5 3 5 36 38 0 38 10 3 6 4 41 43 0 43 10 3 7 4 5 4...

Page 102: ...Sample n 1 Sample n Sample n 1 tSH tLAT tEOC tINT TMS320F28377S TMS320F28376S TMS320F28375S TMS320F28374S SPRS881A AUGUST 2014 REVISED JUNE 2015 www ti com Figure 5 31 ADC Timings for 12 Bit Mode in...

Page 103: ...LE RATIO tEOC tLAT EARLY LATE CYCLES ADCCLKs 0 1 31 31 0 31 31 0 2 2 60 60 0 60 30 0 3 2 5 75 75 0 75 30 0 4 3 90 90 0 90 30 0 5 3 5 104 104 0 104 29 7 6 4 119 119 0 119 29 8 7 4 5 134 134 0 134 29 8...

Page 104: ...n 1 Sample n Sample n 1 tSH tLAT tEOC tINT TMS320F28377S TMS320F28376S TMS320F28375S TMS320F28374S SPRS881A AUGUST 2014 REVISED JUNE 2015 www ti com Figure 5 33 ADC Timings for 16 Bit Mode in Late In...

Page 105: ...49 Temperature Sensor Electrical Characteristics over recommended operating conditions unless otherwise noted PARAMETER MIN TYP MAX UNIT Temperature accuracy 15 C Start up time 500 s ADC acquisition t...

Page 106: ...e includes two comparators two internal voltage reference DACs two digital glitch filters and one ramp generator There are two inputs CMPINxP and CMPINxN Each of these will be internally connected to...

Page 107: ...ital Filter DAC12 DAC12 Comparator Subsystem 4 VDDA or VDAC Digital Filter Digital Filter DAC12 DAC12 CTRIPOUT3H CTRIP3H CTRIP3L CTRIPOUT3L Comparator Subsystem 3 VDDA or VDAC Digital Filter Digital F...

Page 108: ...CONDITIONS MIN TYP MAX UNIT Internal reference 0 VDDA DAC output range V External reference 0 VDAC Static offset error 1 25 25 mV Static gain error 1 2 2 of FSR Static DNL Endpoint corrected 1 4 LSB...

Page 109: ...ovide a known pin voltage when the output buffer is disabled This pulldown resistor cannot be disabled and remains as a passive component on the pin even for other shared pin mux functions Software wr...

Page 110: ...ution 12 Bits Voltage output range 3 0 3 VDDA 0 3 V Capacitive load Output drive capability 100 pF Resistive load Output drive capability 5 k RPD 50 k Reference voltage VDAC or VREFHI 2 4 2 5 or 3 0 V...

Page 111: ...compare logic CTR 0 31 PRD 0 31 CMP 0 31 CTR CMP CTR PRD CTR_OVF OVF APWM mode Delta mode SYNC 4 Capture events CEVT 1 4 APRD shadow 32 32 MODE SELECT TMS320F28377S TMS320F28376S TMS320F28375S TMS320...

Page 112: ...le 5 54 shows the eCAP switching characteristics Table 5 53 eCAP Timing Requirement 1 MIN MAX UNIT Asynchronous 2tc SYSCLK cycles tw CAP Capture input pulse width Synchronous 2tc SYSCLK cycles With in...

Page 113: ...nimal CPU overhead by building the peripheral up from smaller modules with separate resources that can operate together to form a system Some of the highlights of the ePWM type 4 module include comple...

Page 114: ...Active 24 CMPB Shadow 24 HiRes PWM HRPWM CTR PRD or ZERO DCAEVT1 inter DCBEVT1 inter DCAEVT2 inter DCBEVT2 inter EPWMxSYNCI TBCTL SWFSYNC Software Forced Sync DCAEVT1 sync DCBEVT1 sync CMPA Active 24...

Page 115: ...MINT TZINT SOCA SOCB PWM11 CMPC PWM11 CMPD PWM12 CMPC PWM12 CMPD PIE s CLA s EPWMx EPWMCLK EPWMENCLK TBCLKSYNC ADCSOCAOn Select Ckt ADCSOCBOn Select Ckt ADC Wrapper s ePWM and eCAP Sync Chain FLT1 FLT...

Page 116: ...ECAP3 ECAP4 ECAP5 ECAP6 TMS320F28377S TMS320F28376S TMS320F28375S TMS320F28374S SPRS881A AUGUST 2014 REVISED JUNE 2015 www ti com 5 9 2 1 Control Peripherals Synchronization The ePWM and eCAP Synchron...

Page 117: ...Mx output high low 20 ns tw SYNCOUT Sync output pulse width 8tc SYSCLK cycles Delay time trip input active to PWM forced high td PWM tza Delay time trip input active to PWM forced low 25 ns Delay time...

Page 118: ...PxB XDIR EQEPxS EQEPxI QPOSCMP QEINT QFRC 32 QCLR QPOSCTL 16 32 QPOSCNT QPOSMAX QPOSINIT PIE EQEPxINT eQEP Peripheral System Control Registers QCTMR QCPRD 16 16 QCAPCTL EQEPxENCLK SYSCLK To CPU Data B...

Page 119: ...input qualifier 2tc SYSCLK tw IQSW cycles Synchronous 2tc SYSCLK cycles tw STROBH QEP Strobe High time With input qualifier 2tc SYSCLK tw IQSW cycles Synchronous 2tc SYSCLK cycles tw STROBL QEP Strob...

Page 120: ...f the ePWM module NOTE The minimum HRPWMCLK frequency allowed for HRPWM is 60 MHz NOTE When dual edge high resolution is enabled high resolution period mode the PWMxB output is not available for use 5...

Page 121: ...odulator clock rate equals modulator data rate Modulator clock rate running at half the modulator data rate Modulator data is Manchester encoded Modulator clock not required Modulator clock rate is do...

Page 122: ...1 IEH SD2FLT4 IEH SD2FLT3 IEH SD2FLT2 IEH SD2FLT1 IEL SD2FLT4 IEL SD2FLT3 IEL SD2FLT2 IEL Filter R Sinc Filter FILRES SD1_D1 SD2_C4 SD2_D4 SD2_C3 SD2_D3 SD2_C2 SD2_D2 SD2_C1 SD2_D1 SD1_C4 SD1_D4 SD1_C...

Page 123: ...se duration SDx_Cy high 20 tc SDC M1 10 ns tsu SDDV SDCL M1 Setup time SDx_Dy valid before SDx_Cy goes low 5 ns tsu SDDV SDCH M1 Setup time SDx_Dy valid before SDx_Cy goes high 5 ns th SDCL SDD M1 Hol...

Page 124: ...l clock Modulator internal data 1 1 1 1 0 0 1 TMS320F28377S TMS320F28376S TMS320F28375S TMS320F28374S SPRS881A AUGUST 2014 REVISED JUNE 2015 www ti com Figure 5 46 SDFM Timing Diagram Mode 2 Figure 5...

Page 125: ...0 to 8 bytes of data Parity checked configuration and data RAM Individual identifier mask for each message object Programmable FIFO mode for receive message objects Programmable loop back modes for s...

Page 126: ...mit receive and receive transmit mode Data transfer rate of from 10 kbps up to 400 kbps I2 C Fast mode rate One 16 word receive FIFO and one 16 word transmit FIFO One interrupt that can be used by the...

Page 127: ...rupt to CPU PIE TMS320F28377S TMS320F28376S TMS320F28375S TMS320F28374S www ti com SPRS881A AUGUST 2014 REVISED JUNE 2015 Figure 5 48 shows how the I2 C peripheral module interfaces within the device...

Page 128: ...P 0 6 s SDA rise delay Table 5 63 I2 C Switching Characteristics over recommended operating conditions unless otherwise noted PARAMETER TEST CONDITIONS MIN MAX UNIT fSCL SCL clock frequency 0 400 kHz...

Page 129: ...ata clocks Highly programmable internal clock and frame generation Direct interface to industry standard CODECs Analog Interface Chips AICs and other serially connected A D and D A devices Works with...

Page 130: ...6 16 16 Peripheral Bus DRR2 Receive Buffer Peripheral Write Bus Bridge DMA Bus CPU CPU CPU McBSP Transmit Interrupt Select Logic McBSP Receive Interrupt Select Logic TMS320F28377S TMS320F28376S TMS320...

Page 131: ...p time DR valid before CLKR low CLKR int 18 ns CLKR ext 5 M18 th CKRL DRV Hold time DR valid after CLKR low CLKR int 0 ns CLKR ext 3 M19 tsu FXH CKXL Setup time external FSX high before CLKX low CLKX...

Page 132: ...X ext 14 Only applies to first bit DXENA 1 CLKX int P 8 transmitted when in Data CLKX ext Delay 1 or 2 XDATDLY 01b P 14 or 10b modes M8 ten CKXH DX Enable time CLKX high to DXENA 0 CLKX int 0 DX drive...

Page 133: ...M17 M18 M16 M15 M4 M4 M14 M13 M3 M12 M1 M11 M2 M12 RDATDLY 10b DR RDATDLY 01b DR RDATDLY 00b DR FSR ext FSR int CLKR TMS320F28377S TMS320F28376S TMS320F28375S TMS320F28374S www ti com SPRS881A AUGUST...

Page 134: ...racteristics Over Recommended Operating Conditions Unless Otherwise Noted CLKSTP 10b CLKXP 0 MASTER SLAVE NO PARAMETER UNIT MIN MAX MIN MAX M24 th CKXL FXL Hold time FSX low after CLKX low 2P 1 ns M25...

Page 135: ...ended Operating Conditions Unless Otherwise Noted CLKSTP 11b CLKXP 0 MASTER SLAVE NO PARAMETER UNIT MIN MAX MIN MAX M34 th CKXL FXL Hold time FSX low after CLKX low P ns M35 td FXL CKXH Delay time FSX...

Page 136: ...nded Operating Conditions Unless Otherwise Noted CLKSTP 10b CLKXP 1 MASTER SLAVE NO PARAMETER UNIT MIN MAX MIN MAX M43 th CKXH FXL Hold time FSX low after CLKX high 2P 1 ns M44 td FXL CKXL Delay time...

Page 137: ...CLKXP 1 1 MASTER 2 SLAVE NO PARAMETER UNIT MIN MAX MIN MAX M53 th CKXH FXL Hold time FSX low after CLKX high P ns M54 td FXL CKXL Delay time FSX low to CLKX low 2P 1 ns M55 td CLKXH DXV Delay time CLK...

Page 138: ...t Data word length programmable from one to eight bits Optional even odd no parity bit One or two stop bits Four error detection flags parity overrun framing and break detection Two wakeup multiproces...

Page 139: ...XST 5 1 8 TX FIFO registers TX FIFO Interrupt TX Interrupt Logic TXINT SCIFFTX 14 SCICTL1 0 8 RX Interrupt Logic RXINT SCIFFRX 15 RXFFOVF RX Error SCIRXST 7 PE OE FE RX Error To CPU To CPU SCICTL1 1 S...

Page 140: ...its major registers RXSHF register Receiver Shift register Shifts data in from the SCIRXD pin one bit at a time SCIRXBUF register Receiver Data Buffer register Contains data to be read by the CPU Data...

Page 141: ...k phase bits include Falling edge without phase delay SPICLK active high SPI transmits data on the falling edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal Falling e...

Page 142: ...PICTL 3 is high data is transmitted and received a half cycle before the SPICLK transition As a result both controllers send and receive data simultaneously The application software determines whether...

Page 143: ...s Where Clock Phase 0 Section 5 10 5 1 6 High Speed Master Mode External Timings Where Clock Phase 1 Section 5 10 5 1 7 High Speed Slave Mode External Timings Where Clock Phase 0 Section 5 10 5 1 8 Hi...

Page 144: ...1 Valid time SPISIMO data valid after SPICLK tv SPCL SIMO M 0 5tc SPC M 3 low clock polarity 0 5 ns Valid time SPISIMO data valid after SPICLK tv SPCH SIMO M 0 5tc SPC M 3 high clock polarity 1 Setup...

Page 145: ...larity 1 Valid time SPISIMO data valid after tv SPCL SIMO M 0 5tc SPC M 0 5tc LSPCLK 3 SPICLK low clock polarity 0 5 ns Valid time SPISIMO data valid after tv SPCH SIMO M 0 5tc SPC M 0 5tc LSPCLK 3 SP...

Page 146: ...4S SPRS881A AUGUST 2014 REVISED JUNE 2015 www ti com A On the trailing end of the word SPISTE will go inactive except between back to back transmit words in both FIFO and non FIFO modes Figure 5 58 SP...

Page 147: ...3 clock polarity 1 Valid time SPISIMO data valid after SPICLK tv SPCH SIMO M 0 5tc SPC M 3 high clock polarity 0 7 ns Valid time SPISIMO data valid after SPICLK tv SPCL SIMO M 0 5tc SPC M 3 low clock...

Page 148: ...clock polarity 1 Valid time SPISIMO data valid after tv SPCH SIMO M 0 5tc SPC M 0 5tc LSPCLK 3 SPICLK high clock polarity 0 7 ns Valid time SPISIMO data valid after tv SPCL SIMO M 0 5tc SPC M 0 5tc LS...

Page 149: ...ty 1 20 Valid time SPISOMI data valid after SPICLK high tv SPCH SOMI S 0 clock polarity 0 16 ns Valid time SPISOMI data valid after SPICLK low tv SPCL SOMI S 0 clock polarity 1 tsu SIMO SPCL S Setup t...

Page 150: ...olarity 1 20 Valid time SPISOMI data valid after SPICLK low tv SPCL SOMI S 0 clock polarity 0 18 ns Valid time SPISOMI data valid after SPICLK high tv SPCH SOMI S 0 clock polarity 1 tsu SIMO SPCH S Se...

Page 151: ...ock polarity 1 Valid time SPISIMO data valid after SPICLK tv SPCL SIMO M 0 5tc SPC M 1 low clock polarity 0 5 ns Valid time SPISIMO data valid after SPICLK tv SPCH SIMO M 0 5tc SPC M 1 high clock pola...

Page 152: ...lock polarity 1 Valid time SPISIMO data valid after tv SPCL SIMO M 0 5tc SPC M 0 5tc LSPCLK 1 SPICLK low clock polarity 0 5 ns Valid time SPISIMO data valid after tv SPCH SIMO M 0 5tc SPC M 0 5tc LSPC...

Page 153: ...ti com SPRS881A AUGUST 2014 REVISED JUNE 2015 A On the trailing end of the word SPISTE will go inactive except between back to back transmit words in both FIFO and non FIFO modes Figure 5 62 High Spe...

Page 154: ...0 5tc SPC M 1 clock polarity 1 Valid time SPISIMO data valid after SPICLK tv SPCH SIMO M 0 5tc SPC M 1 high clock polarity 0 7 ns Valid time SPISIMO data valid after SPICLK tv SPCL SIMO M 0 5tc SPC M...

Page 155: ...clock polarity 1 Valid time SPISIMO data valid after tv SPCH SIMO M 0 5tc SPC M 0 5tc LSPCLK 1 SPICLK high clock polarity 0 7 ns Valid time SPISIMO data valid after tv SPCL SIMO M 0 5tc SPC M 0 5tc L...

Page 156: ...olarity 1 9 Valid time SPISOMI data valid after SPICLK high tv SPCH SOMI S 0 clock polarity 0 16 ns Valid time SPISOMI data valid after SPICLK low tv SPCL SOMI S 0 clock polarity 1 tsu SIMO SPCL S Set...

Page 157: ...ock polarity 1 9 Valid time SPISOMI data valid after SPICLK low tv SPCL SOMI S 0 clock polarity 0 18 ns Valid time SPISOMI data valid after SPICLK high tv SPCH SOMI S 0 clock polarity 1 tsu SIMO SPCH...

Page 158: ...es control interrupt bulk and isochronous 32 endpoints One dedicated control IN endpoint and one dedicated control OUT endpoint 15 configurable IN endpoints and 15 configurable OUT endpoints Four KB d...

Page 159: ...erential input voltage 0 2 V Table 5 87 USB Output Ports DP and DM Switching Characteristics over recommended operating conditions unless otherwise noted PARAMETER TEST CONDITIONS MIN MAX UNIT VOH D D...

Page 160: ...put and minimize CPU overhead during high speed data transmission All uPP transactions use internal DMA to feed data to or retrieve data from the I O channels Even though there is only one I O channel...

Page 161: ...stream high speed streaming interface with frame START indication Mainstream high speed streaming interface with data ENABLE indication Mainstream high speed streaming interface with synchronization W...

Page 162: ...4 ns 11 th CLKL DV Hold time DATA valid after CLK low 0 8 ns 19 tsu WTV CLKH Setup time WAIT valid before CLK high SDR mode 20 ns 20 th CLKH WTV Hold time WAIT valid after CLK high SDR mode 0 ns 21 ts...

Page 163: ...a8 Data9 3 5 4 7 6 9 8 TMS320F28377S TMS320F28376S TMS320F28375S TMS320F28374S www ti com SPRS881A AUGUST 2014 REVISED JUNE 2015 Figure 5 69 uPP Single Data Rate SDR Receive Timing Figure 5 70 uPP Dou...

Page 164: ...TART ENABLE DATA n 0 WAIT TMS320F28377S TMS320F28376S TMS320F28375S TMS320F28374S SPRS881A AUGUST 2014 REVISED JUNE 2015 www ti com Figure 5 71 uPP Single Data Rate SDR Transmit Timing Figure 5 72 uPP...

Page 165: ...28x to focus on system tasks The TMS320F2837xS supports up to 1MB of onboard flash memory with ECC and up to 164KB of SRAM Two 128 bit secure zones are also available on the CPU for code protection Pe...

Page 166: ...er NMI WDT CPU1 CLA1 Data ROM 4Kx16 CPU1 CLA1 to CPU1 128x16 MSG RAM CPU1 to CPU1 CLA1 128x16 MSG RAM Boot ROM 32Kx16 Non Secure Secure ROM 32Kx16 Secure CPU1 M0 RAM 1Kx16 CPU1 M1 RAM 1Kx16 CPU1 D0 RA...

Page 167: ...0x0000 CFFF Yes GS1 RAM 4K x 16 0x0000 D000 0x0000 DFFF Yes GS2 RAM 4K x 16 0x0000 E000 0x0000 EFFF Yes GS3 RAM 4K x 16 0x0000 F000 0x0000 FFFF Yes GS4 RAM 4K x 16 0x0001 0000 0x0001 0FFF Yes GS5 RAM...

Page 168: ...r G 32K x 16 0x0009 8000 0x0009 FFFF Sector H 32K x 16 0x000A 0000 0x000A 7FFF Sector I 32K x 16 0x000A 8000 0x000A FFFF Sector J 32K x 16 0x000B 0000 0x000B 7FFF Sector K 8K x 16 0x000B 8000 0x000B 9...

Page 169: ...or A 8K x 16 0x0008 0000 0x0008 1FFF Sector B 8K x 16 0x0008 2000 0x0008 3FFF Sector C 8K x 16 0x0008 4000 0x0008 5FFF Sector D 8K x 16 0x0008 6000 0x0008 7FFF Sector E 32K x 16 0x0008 8000 0x0008 FFF...

Page 170: ...sultRegs ADC_RESULT_REGS 0x0000 0B20 0x0000 0B3F Yes Yes AdccResultRegs ADC_RESULT_REGS 0x0000 0B40 0x0000 0B5F Yes Yes AdcdResultRegs ADC_RESULT_REGS 0x0000 0B60 0x0000 0B7F Yes Yes CpuTimer0Regs CPU...

Page 171: ...Yes Sdfm1Regs SDFM_REGS 0x0000 5E00 0x0000 5E7F Yes Yes Sdfm2Regs SDFM_REGS 0x0000 5E80 0x0000 5EFF Yes Yes Peripheral Frame 2 McbspaRegs MCBSP_REGS 0x0000 6000 0x0000 603F Yes Yes McbspbRegs MCBSP_RE...

Page 172: ..._REGS 0x0005 F040 0x0005 F05F DcsmCommonRegs DCSM_COMMON_REGS 0x0005 F070 0x0005 F07F MemCfgRegs MEM_CFG_REGS 0x0005 F400 0x0005 F47F Emif1ConfigRegs EMIF1_CONFIG_REGS 0x0005 F480 0x0005 F49F Emif2Con...

Page 173: ...l Reset Peripheral CPU Select Y GPIO Pin Mapping and Configuration Y Analog System Control Y uPP Message RAMs Y Y Reset Configuration Y Clock and PLL Configuration Y System Configuration Y WD NMIWD LP...

Page 174: ...ister set plus an additional set of floating point unit registers The additional floating point unit registers are the following Eight floating point result registers RnH where n 0 7 Floating point St...

Page 175: ...ation packets or code sections The C28x VCU can perform 8 bit 16 bit 24 bit and 32 bit CRCs For example the VCU can compute the CRC for a block length of 10 bytes in 10 cycles A CRC result register co...

Page 176: ...trol Law Accelerator The CLA is an independent single precision 32 bit floating point unit processor with its own bus structure fetch mechanism and pipeline Eight individual CLA tasks can be specified...

Page 177: ...to start memory transfers periodically The interrupt trigger source for each of the six DMA channels can be configured separately and each channel contains its own independent PIE interrupt to let th...

Page 178: ...ER 3 DMA Trigger Source Selection DMACHSRCSEL1 CHx DMACHSRCSEL2 CHx CHx MODE PERINTSEL x 1 to 6 DMA Trigger Source CPU and DMA Data Path eQEP eCAP CMPSS DAC TMS320F28377S TMS320F28376S TMS320F28375S T...

Page 179: ...6 11 Device Boot Mode GPIO72 GPIO84 BOOT BOOT MODE NO CPU1 BOOT MODE TRST MODE MODE PIN 1 PIN 0 0 Parallel IO 0 0 0 1 SCI Mode 0 0 1 2 Wait Boot Mode 0 1 0 3 Get Mode 0 1 1 4 7 EMU Boot Mode Emulator...

Page 180: ...Table 6 12 shows the GPIO pins used by each peripheral bootloader This device supports two sets of GPIOs for each mode as shown in Table 6 12 Table 6 12 GPIO Pins Used by Each Peripheral Bootloader B...

Page 181: ...RAM blocks which are dedicated to each subsystem and are accessible to its CPU and CLA only are called local shared RAMs LSx RAMs All LSx RAM blocks have parity These memories are secure and have the...

Page 182: ...cess to on chip secure memories The term secure means access to secure memories and resources is blocked The term unsecure means access is allowed for example through a debugging tool such as Code Com...

Page 183: ...onnected to INT14 of the CPU If SYS BIOS is not being used CPU Timer 2 is available for general use CPU Timer 2 can be clocked by any one of the following SYSCLK default Internal zero pin oscillator 1...

Page 184: ...tchdog module is the same as the one on previous TMS320C2000 devices but with an optional lower limit on the time between software resets of the counter This windowed countdown is disabled by default...

Page 185: ...100v2 XDS200 Flash programming tools For a complete listing of development support tools for the processor platform visit the Texas Instruments website at www ti com For technical questions visit http...

Page 186: ...fied development support product TMX and TMP devices and TMDX development support tools are shipped against the following disclaimer Developmental product is intended for internal evaluation purposes...

Page 187: ...P 100 Pin PZP PowerPAD Thermally Enhanced Thin Quad Flatpack HTQFP TEMPERATURE RANGE S 40 C to 105 C T 40 C to 125 C T 40 C to 125 C T Q refers to Q100 qualification for automotive applications J J A...

Page 188: ...d Instruction Sets Reference Guide describes the architecture pipeline and instruction set of the TMU VCU II and FPU accelerators Peripheral Guides SPRU566 TMS320x28xx 28xxx DSP Peripheral Reference G...

Page 189: ...engineers TI Embedded Processors Wiki Texas Instruments Embedded Processors Wiki Established to help developers get started with Embedded Processors from Texas Instruments and to foster innovation and...

Page 190: ...ble information This information is the most current data available for the designated devices This data is subject to change without notice and revision of this document For browser based versions of...

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Page 196: ...WT 337 90 TBD Call TI Call TI 40 to 105 TMS320F28376SPTPS PREVIEW HLQFP PTP 176 40 TBD Call TI Call TI 40 to 125 TMS320F28376SPTPT PREVIEW HLQFP PTP 176 40 TBD Call TI Call TI 40 to 105 TMS320F28376SP...

Page 197: ...efined above Green RoHS no Sb Br TI defines Green to mean Pb Free RoHS compatible and free of Bromine Br and Antimony Sb based flame retardants Br or Sb do not exceed 0 1 by weight in homogeneous mate...

Page 198: ...sponsible for compliance with all legal regulatory and safety related requirements concerning its products and any use of TI components in its applications notwithstanding any applications related inf...

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