ADV
ANCEINFORMA
TION
TMS320F28377S, TMS320F28376S, TMS320F28375S, TMS320F28374S
SPRS881A – AUGUST 2014 – REVISED JUNE 2015
5.10.5.1.6 High-Speed Master Mode External Timings Where Clock Phase = 1
Table 5-82. High-Speed SPI Master Mode External Timings Where ( 1) is Even or
SPIBRR = 0 or 2
NO.
MIN
MAX
UNIT
1
t
c(SPC)M
Cycle time, SPICLK
4t
c(LSPCLK)
128t
c(LSPCLK)
ns
Pulse duration, SPICLK high
t
w(SPCH)M
0.5t
c(SPC)M
– 1
0.5t
c(SPC)M
+ 1
(clock polarity = 0)
2
ns
Pulse duration, SPICLK low
t
w(SPCL))M
0.5t
c(SPC)M
– 1
0.5t
c(SPC)M
+ 1
(clock polarity = 1)
Pulse duration, SPICLK low
t
w(SPCL)M
0.5t
c(SPC)M
– 1
0.5t
c(SPC)M
+ 1
(clock polarity = 0)
3
ns
Pulse duration, SPICLK high
t
w(SPCH)M
0.5t
c(SPC)M
– 1
0.5t
c(SPC)M
+ 1
(clock polarity = 1)
Delay time, SPISIMO data valid to SPICLK
t
d(SIMO-SPCH)M
0.5t
c(SPC)M
– 1
high (clock polarity = 0)
6
ns
Delay time, SPISIMO data valid to SPICLK low
t
d(SIMO-SPCL)M
0.5t
c(SPC)M
– 1
(clock polarity = 1)
Valid time, SPISIMO data valid after SPICLK
t
v(SPCH-SIMO)M
0.5t
c(SPC)M
– 1
high (clock polarity = 0)
7
ns
Valid time, SPISIMO data valid after SPICLK
t
v(SPCL-SIMO)M
0.5t
c(SPC)M
– 1
low (clock polarity = 1)
Setup time, SPISOMI before SPICLK high
t
su(SOMI-SPCH)M
1
(clock polarity = 0)
10
ns
Setup time, SPISOMI before SPICLK low
t
su(SOMI-SPCL)M
1
(clock polarity = 1)
Hold time, SPISOMI data valid after SPICLK
t
h(SPCH-SOMI)M
7
high (clock polarity = 0)
11
ns
Hold time, SPISOMI data valid after SPICLK
t
h(SPCL-SOMI)M
7
low (clock polarity = 1)
Delay time, SPISTE low to SPICLK high (clock
t
d(STE-SPCH)M
0.5t
c(SPC)
– 1
polarity = 0)
23
ns
Delay time, SPISTE low to SPICLK low (clock
t
d(STE-SPCL)M
0.5t
c(SPC)
– 1
polarity = 1)
Delay time, SPICLK low to SPISTE invalid
t
d(SPCL-STE)M
0.5t
c(SPC)
– 1
(clock polarity = 0)
24
ns
Delay time, SPICLK high to SPISTE invalid
t
d(SPCH-STE)M
0.5t
c(SPC)
– 1
(clock polarity = 1)
154
Specifications
Copyright © 2014–2015, Texas Instruments Incorporated
Product Folder Links:
