ADV
ANCEINFORMA
TION
TMS320F28377S, TMS320F28376S, TMS320F28375S, TMS320F28374S
SPRS881A – AUGUST 2014 – REVISED JUNE 2015
6.6
CPU and System Control
6.6.1
C28x Processor
The CPU is a 32-bit fixed-point processor. This device draws from the best features of digital signal
processing; reduced instruction set computing (RISC); and microcontroller architectures, firmware, and
tool sets.
The CPU features include a modified Harvard architecture and circular addressing. The RISC features are
single-cycle instruction execution, register-to-register operations, and modified Harvard architecture. The
microcontroller features include ease of use through an intuitive instruction set, byte packing and
unpacking, and bit manipulation. The modified Harvard architecture of the CPU enables instruction and
data fetches to be performed in parallel. The CPU can read instructions and data while it writes data
simultaneously to maintain the single-cycle instruction operation across the pipeline. The CPU does this
over six separate address/data buses.
For more information on CPU architecture and instruction set, see the
TMS320C28x CPU and Instruction
Set Reference Guide
6.6.1.1
Floating-Point Unit
The C28x plus floating-point (C28x+FPU) processor extends the capabilities of the C28x fixed-point CPU
by adding registers and instructions to support IEEE single-precision floating point operations.
Devices with the C28x+FPU include the standard C28x register set plus an additional set of floating-point
unit registers. The additional floating-point unit registers are the following:
•
Eight floating-point result registers, RnH (where n = 0–7)
•
Floating-point Status Register (STF)
•
Repeat Block Register (RB)
All of the floating-point registers, except the repeat block register, are shadowed. This shadowing can be
used in high-priority interrupts for fast context save and restore of the floating-point registers.
For more information, see the
TMS320C28x Extended Instruction Sets Reference Guide
(
6.6.1.2
Trigonometric Math Unit
The TMU extends the capabilities of a C28x+FPU by adding instructions and leveraging existing FPU
instructions to speed up the execution of common trigonometric and arithmetic operations listed in
Table 6-8. TMU Supported Instructions
INSTRUCTIONS
C EQUIVALENT OPERATION
PIPELINE CYCLES
MPY2PIF32 RaH,RbH
a = b * 2pi
2/3
DIV2PIF32 RaH,RbH
a = b / 2pi
2/3
DIVF32 RaH,RbH,RcH
a = b/c
5
SQRTF32 RaH,RbH
a = sqrt(b)
5
SINPUF32 RaH,RbH
a = sin(b*2pi)
4
COSPUF32 RaH,RbH
a = cos(b*2pi)
4
ATANPUF32 RaH,RbH
a = atan(b)/2pi
4
QUADF32 RaH,RbH,RcH,RdH
Operation to assist in calculating ATANPU2
5
No changes have been made to existing instructions, pipeline or memory bus architecture. All TMU
instructions use the existing FPU register set (R0H to R7H) to carry out their operations. A detailed
explanation of the workings of the FPU can be found in the
TMS320C28x Extended Instruction Sets
Reference Guide
174
Detailed Description
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