ADV
ANCEINFORMA
TION
20
15
SPISIMO
SPISOMI
SPICLK
(clock polarity = 1)
SPICLK
(clock polarity = 0)
SPISIMO Data
Must Be Valid
SPISOMI Data Is Valid
19
25
16
14
12
SPISTE
26
13
TMS320F28377S, TMS320F28376S, TMS320F28375S, TMS320F28374S
SPRS881A – AUGUST 2014 – REVISED JUNE 2015
5.10.5.1.7 High-Speed Slave Mode External Timings Where Clock Phase = 0
Table 5-84. High-Speed SPI Slave Mode External Timings Where Clock Phase = 0
NO.
MIN
MAX
UNIT
12
t
c(SPC)S
Cycle time, SPICLK
4t
c(SYSCLK)
ns
t
w(SPCH)S
Pulse duration, SPICLK high (clock polarity = 0)
2t
c(SYSCLK)
– 1
13
ns
t
w(SPCL)S
Pulse duration, SPICLK low (clock polarity = 1)
2t
c(SYSCLK)
– 1
t
w(SPCL)S
Pulse duration, SPICLK low (clock polarity = 0)
2t
c(SYSCLK)
– 1
14
ns
t
w(SPCH)S
Pulse duration, SPICLK high (clock polarity = 1)
2t
c(SYSCLK)
– 1
t
d(SPCH-SOMI)S
Delay time, SPICLK high to SPISOMI valid (clock polarity = 0)
9
15
ns
t
d(SPCL-SOMI)S
Delay time, SPICLK low to SPISOMI valid (clock polarity = 1)
9
Valid time, SPISOMI data valid after SPICLK high
t
v(SPCH-SOMI)S
0
(clock polarity = 0)
16
ns
Valid time, SPISOMI data valid after SPICLK low
t
v(SPCL-SOMI)S
0
(clock polarity = 1)
t
su(SIMO-SPCL)S
Setup time, SPISIMO before SPICLK low (clock polarity = 0)
5
19
ns
t
su(SIMO-SPCH)S
Setup time, SPISIMO before SPICLK high (clock polarity = 1)
5
Hold time, SPISIMO data valid after SPICLK low
t
h(SPCL-SIMO)S
5
(clock polarity = 0)
20
ns
Hold time, SPISIMO data valid after SPICLK high
t
h(SPCH-SIMO)S
5
(clock polarity = 1)
Setup time, SPISTE valid before SPICLK high
t
su(STE-SPCH)S
2t
c(SYSCLK)
(clock polarity = 0)
25
ns
Setup time, SPISTE valid before SPICLK low
t
su(STE-SPCL)S
2t
c(SYSCLK)
(clock polarity = 1)
t
h(SPCL-STE)S
Hold time, SPISTE invalid after SPICLK low (clock polarity = 0)
2t
c(SYSCLK)
26
ns
t
h(SPCH-STE)S
Hold time, SPISTE invalid after SPICLK high (clock polarity = 1)
2t
c(SYSCLK)
Figure 5-64. High-Speed SPI Slave Mode External Timing (Clock Phase = 0)
156
Specifications
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