ADV
ANCEINFORMA
TION
(
)
CLKSRG
CLKG =
1 + CLKGDV
TMS320F28377S, TMS320F28376S, TMS320F28375S, TMS320F28374S
SPRS881A – AUGUST 2014 – REVISED JUNE 2015
5.10.3 Multichannel Buffered Serial Port (McBSP)
The McBSP module has the following features:
•
Compatible to McBSP in TMS320C28x/TMS320F28x DSP devices
•
Full-duplex communication
•
Double-buffered data registers that allow a continuous data stream
•
Independent framing and clocking for receive and transmit
•
External shift clock generation or an internal programmable frequency shift clock
•
8-bit data transfer mode can be configured to transmit with LSB or MSB first
•
Programmable polarity for both frame synchronization and data clocks
•
Highly programmable internal clock and frame generation
•
Direct interface to industry-standard CODECs, Analog Interface Chips (AICs), and other serially
connected A/D and D/A devices
•
Works with SPI-compatible devices
•
The following application interfaces can be supported on the McBSP:
–
T1/E1 framers
–
IOM-2 compliant devices
–
AC97-compliant devices (the necessary multiphase frame synchronization capability is provided.)
–
IIS-compliant devices
–
SPI
•
McBSP clock rate,
where CLKSRG source could be LSPCLK, CLKX, or CLKR. Serial port performance is limited by I/O
buffer switching speed. Internal prescalers must be adjusted such that the peripheral speed is less
than the I/O buffer speed limit.
Copyright © 2014–2015, Texas Instruments Incorporated
Specifications
129
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