ADV
ANCEINFORMA
TION
CPU1.CLA1
CPU1.DMA
Arbi
t
Arbiter X
SECMSEL.VBUS32_2
uPP
(Universal
Parallel Port)
RX-DATARAM
512 Byte
(Dual Port
Memory)
TX-DATARAM
512 Byte
(Dual Port
Memory)
Arbi
t
CPU1
Arbiter Y
0
1
Arbi
t
Arbiter Y
CPU1
CPU1.CLA1
CPU1
CPU1.CLA1
WRITE
READ
I/O Interface
uPP DMA READ
uPP DMA WRITE
TMS320F28377S, TMS320F28376S, TMS320F28375S, TMS320F28374S
SPRS881A – AUGUST 2014 – REVISED JUNE 2015
5.10.7 Universal Parallel Port (uPP)
The uPP is a high-speed parallel interface with dedicated data lines and minimal control signals. It is
designed to interface cleanly with high-speed ADCs or DACs with 8-bit data width. It can also be
interconnected with field-programmable gate arrays (FPGAs) or other uPP devices to achieve high-speed
digital data transfer. It can operate in receive mode or transmit mode (simplex mode).
The uPP includes an internal DMA controller to maximize throughput and minimize CPU overhead during
high-speed data transmission. All uPP transactions use internal DMA to feed data to or retrieve data from
the I/O channels. Even though there is only one I/O channel, the DMA controller includes two DMA
channels to support data interleave mode, in which all DMA resources service a single I/O channel.
On this device, the uPP is the dedicated resource for the CPU1 subsystem. CPU1, CPU1.CLA1, and
CPU1.DMA have access to this module. Two dedicated 512-byte data RAMs (also known as MSG RAMs)
are tightly coupled with the uPP module (one for each, TX and RX). These data RAMs are used to store
the bulk of data to avoid frequent interruptions to the CPU. Only CPU1 and CPU1.CLA1 have access to
these data RAMs.
shows the integration of the uPP on this device.
Figure 5-67. uPP Integration
NOTE
On some TI devices, the uPP IP is also called the Radio Peripheral Interface (RPI) module.
160
Specifications
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