Texas Instruments Delfino TMS320F28374S, Manual

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ADV
ANCEINFORMA
TION
TMS320F28377S, TMS320F28376S, TMS320F28375S, TMS320F28374S
www.ti.com SPRS881A – AUGUST 2014 – REVISED JUNE 2015
Table 4-1. Signal Descriptions (continued)
TERMINAL
ZWT PTP PZP
I/O/Z
(1)
DESCRIPTION
MUX
NAME BALL PIN PIN
POSITION
NO. NO. NO.
INTERNAL VOLTAGE REGULATOR CONTROL
Internal voltage regulator enable with internal pulldown.
VREGENZ J18 119 64 I The internal VREG is not supported and must be
disabled. Connect VREGENZ to V
DDIO
.
ANALOG, DIGITAL, AND I/O POWER
E9 16 16
E11 21 39
F9 61 45
F11 76 63
G14 117 71
G15 126 78
1.2-V digital logic power pins. TI recommends placing a
decoupling capacitor near each V
DD
pin with a minimum
J14 137 84
V
DD
total capacitance of approximately 20 uF. The exact
J15 153 89
value of the decoupling capacitance should be
determined by your system voltage regulation solution.
K5 158 95
K6 169 –
P10 – –
P13 – –
R10 – –
R13 – –
R11 72 41
3.3-V Flash power pin. Place a minimum 0.1-µF
V
DD3VFL
decoupling capacitor on each pin.
R12 – –
P6 36 18
3.3-V analog power pins. Place a minimum 2.2-µF
V
DDA
decoupling capacitor on each pin.
R6 54 38
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Terminal Configuration and Functions 37
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