TXMC638 User Manual Issue 1.0.2
Page 79 of 86
# Timings
create_clock -name adc_bclk_2 -period 9.5238095238095238095238095238095 [get_ports {ADC_SCKOUT_P[2]}]
set_input_delay -clock adc_bclk_2 -min 0 [get_ports {ADC_SDO1_P[2]}]
set_input_delay -clock adc_bclk_2 -max 2 [get_ports {ADC_SDO1_P[2]}]
set_input_delay -clock adc_bclk_2 -min 0 [get_ports {ADC_SDO2_P[2]}]
set_input_delay -clock adc_bclk_2 -max 2 [get_ports {ADC_SDO2_P[2]}]
set_clock_groups -asynchronous -group {adc_bclk_2} -group {USER_CLKA};
set_max_delay 10 -datapath_only -from {adc_bclk_2} -to {USER_CLKA};
set_max_delay 10 -datapath_only -from {USER_CLKA} -to {adc_bclk_2};
# ADC #3
set_property SLEW FAST [get_ports {ADC_CNV_n[3]}]
set_property IOSTANDARD LVCMOS25 [get_ports {ADC_CNV_n[3]}]
set_property PACKAGE_PIN Y20 [get_ports {ADC_CNV_n[3]}]
set_property IOSTANDARD LVDS_25 [get_ports {ADC_SCK_P[3]}]
# External Termination
set_property PACKAGE_PIN AE22 [get_ports {ADC_SCK_P[3]}]
set_property IOSTANDARD LVDS_25 [get_ports {ADC_SCK_N[3]}]
# External Termination
set_property PACKAGE_PIN AF22 [get_ports {ADC_SCK_N[3]}]
set_property IOSTANDARD LVDS_25 [get_ports {ADC_SCKOUT_P[3]}]
set_property DIFF_TERM TRUE [get_ports {ADC_SCKOUT_P[3]}]
set_property PACKAGE_PIN H17 [get_ports {ADC_SCKOUT_P[3]}]
set_property IOSTANDARD LVDS_25 [get_ports {ADC_SCKOUT_N[3]}]
set_property DIFF_TERM TRUE [get_ports {ADC_SCKOUT_N[3]}]
set_property PACKAGE_PIN H18 [get_ports {ADC_SCKOUT_N[3]}]
set_property SLEW FAST [get_ports {ADC_SDO1_P[3]}]
set_property IOSTANDARD LVDS_25 [get_ports {ADC_SDO1_P[3]}]
set_property DIFF_TERM TRUE [get_ports {ADC_SDO1_P[3]}]
set_property PACKAGE_PIN H16 [get_ports {ADC_SDO1_P[3]}]
set_property SLEW FAST [get_ports {ADC_SDO1_N[3]}]
set_property IOSTANDARD LVDS_25 [get_ports {ADC_SDO1_N[3]}]
set_property DIFF_TERM TRUE [get_ports {ADC_SDO1_N[3]}]
set_property PACKAGE_PIN G16 [get_ports {ADC_SDO1_N[3]}]
set_property SLEW FAST [get_ports {ADC_SDO2_P[3]}]
set_property IOSTANDARD LVDS_25 [get_ports {ADC_SDO2_P[3]}]
set_property DIFF_TERM TRUE [get_ports {ADC_SDO2_P[3]}]
set_property PACKAGE_PIN G19 [get_ports {ADC_SDO2_P[3]}]
set_property SLEW FAST [get_ports {ADC_SDO2_N[3]}]
set_property IOSTANDARD LVDS_25 [get_ports {ADC_SDO2_N[3]}]
set_property DIFF_TERM TRUE [get_ports {ADC_SDO2_N[3]}]
set_property PACKAGE_PIN F20 [get_ports {ADC_SDO2_N[3]}]
# Timings
create_clock -name adc_bclk_3 -period 9.5238095238095238095238095238095 [get_ports {ADC_SCKOUT_P[3]}]
set_input_delay -clock adc_bclk_3 -min 0 [get_ports {ADC_SDO1_P[3]}]
set_input_delay -clock adc_bclk_3 -max 2 [get_ports {ADC_SDO1_P[3]}]
set_input_delay -clock adc_bclk_3 -min 0 [get_ports {ADC_SDO2_P[3]}]
set_input_delay -clock adc_bclk_3 -max 2 [get_ports {ADC_SDO2_P[3]}]
set_clock_groups -asynchronous -group {adc_bclk_3} -group {USER_CLKA};
set_max_delay 10 -datapath_only -from {adc_bclk_3} -to {USER_CLKA};
set_max_delay 10 -datapath_only -from {USER_CLKA} -to {adc_bclk_3};
# ADC #4
set_property SLEW FAST [get_ports {ADC_CNV_n[4]}]
set_property IOSTANDARD LVCMOS25 [get_ports {ADC_CNV_n[4]}]
set_property PACKAGE_PIN M24 [get_ports {ADC_CNV_n[4]}]
set_property IOSTANDARD LVDS_25 [get_ports {ADC_SCK_P[4]}]
# External Termination
set_property PACKAGE_PIN U26 [get_ports {ADC_SCK_P[4]}]
