TXMC638 User Manual Issue 1.0.2
Page 24 of 86
User FPGA Highlights
7.2
The FPGA is a Kintex-7 XC7K160T, XC7K325T or XC7K410T FPGA. Each Kintex-7 FPGA in a FBG676
package provides eight GTX four for high speed back I/O communication and four for the PCI Express
interface (x4 Linkage).
KIntex-7
Logic
Cells
Slices
DSP
Slices
Block RAM (Kb)
CMTs
GTXs
(MGT)
XADC
Block
18 Kb
36 Kb
max(Kb)
XC7K160T
162,240
25.350
600
650
325
11,700
8
8
1
XC7K325T
326,080
50.950
840
890
445
16,020
10
8
1
XC7K410T
406,720
63.550
1540
1590
795
28,620
10
8
1
Table 7-1 : TXMC638 FPGA Feature Overview
PCI Express Highlights:
x
Compliant to the PCI Express Base Specification 2.1 with Endpoint and Root Port capability.
x
Supports Gen1 (2.5 Gb/s) and Gen2 (5 Gb/s)
XADC Highlights:
XADC (Analog-to-Digital Converter)
On-chip temperature (±4°C max error) and power supply (±1% max error) sensors
x
Continuous JTAG access to ADC measurements
x
Internal access to all internal sensors of the Kintex-7
The board supports JTAG, master serial mode configuration from SPI-Flash or Slave Select MAP
configuration for the User FPGA (Kintex-7) via Board Configuration Controller (BCC).
The User FPGA is equipped with 6 I/O banks and 8 GTX (Gigabit Transceiver).
Bank
VCCO
VREF
Signals
Note
Bank 0
3.3V
none
SPI Configuration with or without
Tandem configuration
Slave Select Map Configuration
GPIOs
Bank 14
3.3V
none
Bank 12
2.5V
none
ser. ADC Interface
Back I/O
diff. digital Front I/O (Ch.0 & 1)
Bank 13
2.5V
none
Bank 15
2.5V
none
Bank 16
2.5V
none
Bank 32
1.35V
0.625V
DDR3 Memory Interface
1GB
diff. digital Front I/O (Ch. 2)
Bank 33
1.35V
0.625V
Bank 34
1.35V
0.625V
Bank 115
Optional used for Back I/O link
Bank 116
PCIe X4 Interface to PCIe Switch Device
Table 7-2 : FPGA Bank Usage
