TXMC638 User Manual Issue 1.0.2
Page 6 of 86
List of Figures
FIGURE 1-1 : BLOCK DIAGRAM......................................................................................................................8
FIGURE 4-1 : PCIE/PCI DEVICE TOPOLOGY...............................................................................................12
FIGURE 7-1 : FPGA BLOCK DIAGRAM.........................................................................................................23
FIGURE 7-2 : GTP BLOCK DIAGRAM ...........................................................................................................25
FIGURE 7-3 : USER JTAG-CHAIN ................................................................................................................31
FIGURE 7-4 : TEWS FACTORY JTAG-CHAIN ..............................................................................................31
FIGURE 7-5 : FPGA CLOCK SOURCES.......................................................................................................36
FIGURE 7-6 : ANALOG INPUT SECTION.....................................................................................................47
FIGURE 7-7 : ANALOG INPUT BLOCK DIAGRAM.......................................................................................47
FIGURE 7-8 : DIGITAL ADC TO FPGA INTERFACE....................................................................................53
FIGURE 7-9 : TIMING DIAGRAM LTC2323-16 .............................................................................................53
FIGURE 7-10: BLOCK DIAGRAM DIFFERENTIAL INPUTS..........................................................................54
FIGURE 7-11: CONFIGURATION FPGA SLAVE ADDRESS ........................................................................55
FIGURE 7-12: CONFIGURATION FPGA START AND STOP CONDITION..................................................55
FIGURE 7-13: CONFIGURATION FPGA OUTPUT ACKNOWLEDGE ..........................................................56
FIGURE 7-14: CONFIGURATION FPGA SLAVE ACCESS ...........................................................................56
FIGURE 7-15: TXMC638 WITH HEATSINK ....................................................................................................58
FIGURE 9-1 : FPGA JTAG CONNECTOR X4 ...............................................................................................63
FIGURE 10-1: PIN ASSIGNMENT P14 BACK I/O CONNECTOR TXMC638 ................................................68
FIGURE 10-2: PIN ASSIGNMENT P16 BACK I/O CONNECTOR TXMC638 ................................................69
