TXMC638 User Manual Issue 1.0.2
Page 39 of 86
Back I/O Interface
7.7
P14 Back I/O Pins of the TXMC638 are direct routed to the User FPGA (Kintex-7). The I/O functions of these
FPGA pins are directly dependent on the configuration of the FPGA.
The Kintex-7 VCCO voltage is set to 2.5V, so only the 2.5V I/O standards LVCMOS25, LVTTL25 and
LVDS_25 are possible for using on TXMC638 back I/O interface.
Signal Name
Pin
Number
Direction
IO Standard
for example
IO
Bank
B
C12
IN/OUT
LVDS_25
16
BACK_IO0-
C11
IN/OUT
LVDS_25
16
B
E11
IN/OUT
LVDS_25
16
BACK_IO1-
D11
IN/OUT
LVDS_25
16
B
E10
IN/OUT
LVDS_25
16
BACK_IO2-
D10
IN/OUT
LVDS_25
16
B
G11
IN/OUT
LVDS_25
16
BACK_IO3-
F10
IN/OUT
LVDS_25
16
B
A9
IN/OUT
LVDS_25
16
BACK_IO4-
A8
IN/OUT
LVDS_25
16
B
B10
IN/OUT
LVDS_25
16
BACK_IO5-
A10
IN/OUT
LVDS_25
16
B
A13
IN/OUT
LVDS_25
16
BACK_IO6-
A12
IN/OUT
LVDS_25
16
B
C9
IN/OUT
LVDS_25
16
BACK_IO7-
B9
IN/OUT
LVDS_25
16
B
B14
IN/OUT
LVDS_25
16
BACK_IO8-
A14
IN/OUT
LVDS_25
16
B
B12
IN/OUT
LVDS_25
16
BACK_IO9-
B11
IN/OUT
LVDS_25
16
BA
B15
IN/OUT
LVDS_25
16
BACK_IO10-
A15
IN/OUT
LVDS_25
16
BA
D9
IN/OUT
LVDS_25
16
BACK_IO11-
D8
IN/OUT
LVDS_25
16
BA
C14
IN/OUT
LVDS_25
16
BACK_IO12-
C13
IN/OUT
LVDS_25
16
BA
D14
IN/OUT
LVDS_25
16
BACK_IO13-
D13
IN/OUT
LVDS_25
16
BA
F9
IN/OUT
LVDS_25
16
BACK_IO14-
F8
IN/OUT
LVDS_25
16
BA
E13
IN/OUT
LVDS_25
16
BACK_IO15-
E12
IN/OUT
LVDS_25
16
BA
G10
IN/OUT
LVDS_25
16
