TXMC638 User Manual Issue 1.0.2
Page 26 of 86
The MGT clock MGTREFCLK0_116 (PCI Express Endpoint Block clock reference) of 100 MHz is generated
by the PI7C9X2G312GP PCIe Switch. The MGTREFCLK0_115 is connected to a 156.25 MHz clock output
of the Si5338 low jitter clock generator. MGTREFCLK1_115 and MGTREFCLK1_116 are not used on the
TXMC638.
GTP
Signal
FPGA
Pins
Connected to
MGTREFCLK0_115
CLK_MGT
H6 / H5
156.25 MHz
Si5338
Clock Generator
MGTREFCLK1_115
not used
K6 / K5
not connected
MGTREFCLK0_116
REFCLKO2
D6 / D5
100 MHz
PI7C9X2G312GP
PCIe Switch
MGTREFCLK1_116
not used
F6 / F5
not connected
Table 7-4 : Multi Gigabit Transceiver Reference Clocks
