TXMC638 User Manual Issue 1.0.2
Page 56 of 86
TXMC638 Configuration FPFA I2C Slave Output Acknowledge
SCL
Data In
Start
Data Out
Acknowledge
Figure 7-13: Configuration FPGA Output Acknowledge
7.11.2 Read Operation
The TXMC638 Configuration FPGA provides only one 32 bit register which could be read from User FPGA
via a I2C Interface.
The read operation starts with a I2C start condition followed by a 7 bit slave address. The read/write bit in the
device address byte is set to one. The configuration FPGA acknowledged the address and began to transmit
all four data byte of the TXM638 Serial Number Register. Each byte must be acknowledged. The sequence
must be completed with a stop condition by the User FPGA.
0
1
1
1
0
0
1
1
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
S
T
O
P
S
T
A
R
T Slave Address
R
E
A
D
R
/
W
L
S
B
M
S
B
SNr. low Byte
SNr. hight Byte
Figure 7-14: Configuration FPGA Slave Access
7.11.3 Write Operation
A I2C write operation is not implemented.
