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Tews Technologies TXMC638, User Manual

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Tews Technologies TXMC638 User Manual Download Page 41

TXMC638 User Manual Issue 1.0.2

Page 41 of 86

Memory

7.8

The TXMC638 is equipped with a 1 GB, 32 bit wide DDR3 SDRAM and a 128-Mbit non-volatile SPI-Flash. 
The SPI-Flash can also be used as configuration memory.

7.8.1 DDR3 SDRAM

The TXMC638 provides two MT41… (96-ball) DDR3 memory devices. The memory is accessible through a
Memory Interface Controller Block IP in bank 32, 33 and 34 of the User FPGA.

Signal

DDR3 Pin

Termination

Memory Devices

Pin

Name

A0

AC8

ȍ977

N3

A0

A1

AA7

ȍ977

P7

A1

A2

AA8

ȍ977

P3

A2

A3

AF7

ȍ977

N2

A3

A4

AE7

ȍ977

P8

A4

A5

W8

ȍ977

P2

A5

A6

V9

ȍ977

R8

A6

A7

Y10

ȍ977

R2

A7

A8

Y11

ȍ977

T8

A8

A9

Y7

ȍ977

R3

A9

A10

Y8

ȍ977

L7

A10

A11

V7

ȍ977

R7

A11

A12

V8

ȍ977

N7

A12

A13

W11

ȍ977

T3

NC/A13

A14

V11

ȍ977

T7

NC/A14

BA0

AC7

ȍ977

M2

BA0

BA1

AB7

ȍ977

N8

BA1

BA2

AD8

ȍ977

M3

BA2

RAS#

AA9

ȍ977

J3

RAS#

CAS#

AB9

ȍ977

K3

CAS#

WE#

AC9

ȍ977

L3

WE#

RESET#

W10

Nȍ*1'

T2

RESET#

CKE[0]

AB12

Nȍ*1'

K9

CKE

ODT[0]

AC12

Nȍ*1'

K1

ODT

DM_0

AE17

ODT

E7

LDM

DM_1

AA14

ODT

D3

UDM

DM_2

U6

ODT

E7

LDM

DM_3

Y3

ODT

D3

UDM

DQ0

AF17

ODT

E3

DQ0

DQ1

AF14

ODT

F7

DQ1

DQ2

AF15

ODT

F2

DQ2

DQ3

AD15

ODT

F8

DQ3

Summary of Contents for TXMC638

Page 1: ...onfigurable FPGA with 24 x 16 Bit Analog Input Version 1 0 User Manual Issue 1 0 2 October 2017 TEWS TECHNOLOGIES GmbH Am Bahnhof 7 25469 Halstenbek Germany Phone 49 0 4101 4058 0 Fax 49 0 4101 4058 1...

Page 2: ...effort to ensure that this manual is accurate and complete However TEWS TECHNOLOGIES GmbH reserves the right to change the product described in this document at any time without notice TEWS TECHNOLOG...

Page 3: ...Date 1 0 0 Initial issue October 2016 1 0 1 Additions to the technical specifiction and correction of the MGT Connections Table User FPGA Configuration Flow Charts enhanced November 2016 1 0 2 Insert...

Page 4: ...5 ISP Control Register 0xE0 19 5 2 6 ISP Configuration Register 0xE4 19 5 2 7 ISP Command Register 0xE8 20 5 2 8 ISP Status Register 0xEC 20 5 2 9 TXMC638 Serial Number 0xF8 21 5 2 10 BCC FPGA Code V...

Page 5: ...ation 55 7 11 7 11 1 Device Addressing and Operation 55 7 11 2 Read Operation 56 7 11 3 Write Operation 56 On Board Indicators 57 7 12 Thermal Management 58 7 13 8 DESIGN HELP 59 Board Reference Desig...

Page 6: ...BLOCK DIAGRAM 47 FIGURE 7 8 DIGITAL ADC TO FPGA INTERFACE 53 FIGURE 7 9 TIMING DIAGRAM LTC2323 16 53 FIGURE 7 10 BLOCK DIAGRAM DIFFERENTIAL INPUTS 54 FIGURE 7 11 CONFIGURATION FPGA SLAVE ADDRESS 55 FI...

Page 7: ...7 1 TXMC638 FPGA FEATURE OVERVIEW 24 TABLE 7 2 FPGA BANK USAGE 24 TABLE 7 3 MGT CONNECTIONS 25 TABLE 7 4 MULTI GIGABIT TRANSCEIVER REFERENCE CLOCKS 26 TABLE 7 5 AVAILABLE FPGA CLOCKS 37 TABLE 7 6 FPG...

Page 8: ...VCMOS25 or as 32 differential LVDS25 interface Additionally the TXMC638 provides three 100 Ohm terminated ac coupled differential inputs with wide Input voltage range The User FPGA is connected to a 1...

Page 9: ...PGA LCMXO2 7000HC Lattice ADC LTC2323IUFD 16 Linear Technologies I O Interface Number of analog Input 24 differential 16 bit Inputs Analog Input Voltage diff VINMAX allowed voltage between input pins...

Page 10: ...F and MIL HDBK 217F Notice 2 Environment GB 20 C The MTBF calculation is based on component FIT rates provided by the component suppliers If FIT rates are not available MIL HDBK 217F and MIL HDBK 217F...

Page 11: ...ther handling of the TXMC638 has to be done in an ESD EOS protected Area Thermal Considerations 3 2 Forced air cooling is recommended during operation Without forced air cooling damage to the device c...

Page 12: ...Connector communicating with the host system P15 XC7KxxxT 2 PCIe to PCI Bridge x4PCIe x1PCIe x4PCIe PI7C9X2G312GP XIO2001 LCMXO2 User FPGA BoardConfiguration Controller FPGA Figure 4 1 PCIe PCI Devic...

Page 13: ...or Local Address Space 1 Y FFFFFF00 0x18 PCI Base Address 2 for Local Address Space 2 N 00000000 0x1C PCI Base Address 3 for Local Address Space 3 N 00000000 0x20 PCI Base Address 4 for Local Address...

Page 14: ...eserved 0xCC Reserved 0xD0 User FPGA Configuration Control Status Register 32 0xD4 User FPGA Configuration Data Register Slave SelectMAP 32 0xD8 Reserved 0xDC Reserved 0xE0 ISP Control Register SPI 32...

Page 15: ...tarted The data must cover a complete SPI Flash memory page For ISP read instructions the data can be read zero based from the ISP Data Space after the instruction is done The data is passed for a com...

Page 16: ...uest Event Interrupt Enable 0 Interrupt Disabled 1 Interrupt Enabled While disabled the corresponding bit in the Interrupt Status Register is 0 Disabling interrupts does not affect the interrupt sourc...

Page 17: ...is high in case of successful FPGA configuration 0 FPGA DONE Pin Level is Low not active 1 FPGA DONE Pin Level is High active R x 1 FP_RE_CFG After power up the FPGA automatically configures from the...

Page 18: ...for direct Slave Select Map FPGA programming mode Must be written with 32 bit FPGA programming data until the FPGA Done pin goes high after the actual programming data writing some dummy data may be r...

Page 19: ...set to 0 when the User FPGA should configure from the SPI Flash e g after SPI Flash programming in Master Serial SPI mode Note that for ISP Direct FPGA Programming the FPGA must first be set to Slave...

Page 20: ...ISP Command Register 5 2 8 ISP Status Register 0xEC Bit Symbol Description Access Reset Value 31 2 Reserved 0x00_0000 1 ISP_SPI_ INS_BSY ISP SPI Instruction Busy Status Set Cleared automatically by H...

Page 21: ...umber can also be read via an I2C interface from User FPGA KIntex 7 5 2 10 BCC FPGA Code Version 0xFC Bit Symbol Description Access Reset Value 31 0 CODE_VER The value shows the BCC Firmware code vers...

Page 22: ...I Instruction Done Event Interrupt Event based interrupt that becomes active when the ISP SPI Instruction Busy status bit changes from busy to not busy x ISP SPI Page Data Done Event Interrupt Event b...

Page 23: ...160T XC7K325T XC7K410T DDR3 Interface Configuration BackI O ADCInterface VCCO 2 5V VCCO 1 35V VCCO 3 3V PCI Express P16MGTs PCIeSwitch SPI Flash FPGAConf Data Digital Front I O 3xdiff I O P16BackI O 4...

Page 24: ...Digital Converter On chip temperature 4 C max error and power supply 1 max error sensors x Continuous JTAG access to ADC measurements x Internal access to all internal sensors of the Kintex 7 The boa...

Page 25: ...38 Ref Clock 156 25MHz XMC P16 MGT Bank 115 Figure 7 2 GTP Block Diagram GTP Signal FPGA Pins Connected to MGTXTXP0_115 MGTTX0 P2 P1 connected to XMC P16 MGTRX0 R4 R3 MGTXTXP1_115 MGTTX1 M2 M1 MGTRX1...

Page 26: ...Hz clock output of the Si5338 low jitter clock generator MGTREFCLK1_115 and MGTREFCLK1_116 are not used on the TXMC638 GTP Signal FPGA Pins Connected to MGTREFCLK0_115 CLK_MGT H6 H5 156 25 MHz Si5338...

Page 27: ...perform the configuration as quick as possible The PCIe specification dictates that a PCI device must be accessible after 100ms 120ms To speed up the SPI Configuration the following points must be tak...

Page 28: ...Low FPGA is not configured 1 FPGA DONE Pin Level is High FPGA is configured The link between the PCIe Switch and the Kintex 7 must be enabled A successful User FPGA configuration is indicated with FP...

Page 29: ...Status Register to 0 Check response of the Kintex 7 by reading the FPGA INIT_B pin value While the FPGA INIT_B pin Level is low the Kintex 7 isn t ready for configuration If FPGA INIT_B pin high then...

Page 30: ...NX User Guide ug470 7 Series FPGAs Configuration for more information about Configuration Details and Configuration Data File Formats The following BitGen options are mandatory for the Slave Select Ma...

Page 31: ...back or in system diagnostics with Vivado Logic Analyzer the JST XRS Debug Connector can be used to access the JTAG chain Also an indirect SPI PROM programming is possible via JTAG Chain TEWS provides...

Page 32: ...the ISP Configuration Register Start the Instruction with ISP Command Register Wait on ISP SPI Instruction Done or ISP SPI Page Data Done for next write instruction Process should be repeated until a...

Page 33: ...e FPGA is not configured or if it is possible that the FPGA accesses the SPI flash during BCC access set FP_RE_CFG 0b1 Link must be set to disable previously Set the Chip Erase instruction in the ISP...

Page 34: ...ly Write the Sector Address to the ISP Configuration Register Set the Chip Erase instruction in the ISP Configuration Register Start the Instruction with ISP Command Register Wait on ISP SPI Instructi...

Page 35: ...Command Register Wait on ISP SPI Instruction Done or ISP SPI Page Data Done for next write instruction Read one page of SPI Data from In Circuit Programming Data Space and write to Data file Process c...

Page 36: ...e following figure depicts an abstract User FPGA clock flow Si514 prog XO Si5338ClockGenerator BCC Kintex 7 DDR3 PCIeSwitch Bank 33 32MHz Oscillator 200 MHz REF_CLK 88 889 MHz MCB_CLK 156 25 MHz 100MH...

Page 37: ...2323 Diff Clock ADC Ch 3 and 4 IO_L14P N_T2_SRCC_12 AC23 AC24 LTC2323 Diff Clock ADC Ch 5 and 6 IO_L14P N_T2_SRCC_15 H17 H18 LTC2323 Diff Clock ADC Ch 7 and 8 IO_L12P N_T1_MRCC_15 F17 E17 LTC2323 Diff...

Page 38: ...open drain buffer The same I2C interface is used for the calibration data prom SPI PROM Signal Bank VCCO Pin Description Kintex 7 FPGA_SCL 14 3 3V F25 Serial clock FPGA_SDA 14 3 3V G26 Serial data Tab...

Page 39: ...BACK_IO3 G11 IN OUT LVDS_25 16 BACK_IO3 F10 IN OUT LVDS_25 16 BACK_IO4 A9 IN OUT LVDS_25 16 BACK_IO4 A8 IN OUT LVDS_25 16 BACK_IO5 B10 IN OUT LVDS_25 16 BACK_IO5 A10 IN OUT LVDS_25 16 BACK_IO6 A13 IN...

Page 40: ...G14 IN OUT LVDS_25 16 BACK_IO23 J13 IN OUT LVDS_25 16 BACK_IO23 H13 IN OUT LVDS_25 16 BACK_IO24 P16 IN OUT LVDS_25 13 BACK_IO24 N17 IN OUT LVDS_25 13 BACK_IO25 N18 IN OUT LVDS_25 13 BACK_IO25 M19 IN...

Page 41: ...ory Devices Pin Name A0 AC8 977 N3 A0 A1 AA7 977 P7 A1 A2 AA8 977 P3 A2 A3 AF7 977 N2 A3 A4 AE7 977 P8 A4 A5 W8 977 P2 A5 A6 V9 977 R8 A6 A7 Y10 977 R2 A7 A8 Y11 977 T8 A8 A9 Y7 977 R3 A9 A10 Y8 977 L...

Page 42: ...DT E3 DQ0 DQ17 U2 ODT F7 DQ1 DQ18 U1 ODT F2 DQ2 DQ19 V3 ODT F8 DQ3 DQ20 W3 ODT H3 DQ4 DQ21 U7 ODT H8 DQ5 DQ22 V6 ODT G2 DQ6 DQ23 V4 ODT H7 DQ7 DQ24 Y2 ODT D7 DQ8 DQ25 V2 ODT C3 DQ9 DQ26 V1 ODT C8 DQ10...

Page 43: ...Device 01 DDR3 Memory Device 02 Both DDR3 Memory Devices 01 02 For details regarding the DDR3 SDRAM interface please refer to XILINX Memory Interface Generator Documentation Xilinx UG586 Zynq 7000 AP...

Page 44: ...t environment and build such a possible basis If system specific calibration data are needed the calibration of the entire system can be done by user and the I2C EEPROM could be used as a possible mem...

Page 45: ...0x000 ADC Channel 1 Offsetcorr High Byte 8 0x001 ADC Channel 1 Offsetcorr Low Byte 8 0x002 ADC Channel 1 Gaincorr High Byte 8 0x003 ADC Channel 1 Gaincorr Low Byte 8 0x004 ADC Channel 2 Offsetcorr Hi...

Page 46: ...1 corr corr Offset Gain Value is the corrected result Reading is the data read from the ADC Data Register Gaincorr and Offsetcorr are the ADC correction factors from the Calibration Data ROM stored f...

Page 47: ...nput voltage on each input pin 5V differential voltage range and also the wide common mode voltage range of 7 5 V two stage input operational amplifiers for input impedance conversion and gain adaptio...

Page 48: ...of ground related voltages that can be tied to the ADC differential inputs This results in an extended input voltage range since the ADC measures the voltage between the differential inputs VIN and VI...

Page 49: ...CNV_N_00 12 2 5V AB26 Convert Signal for ADC Channel 1 and 2 Signal Bank VCCO Pin Description SCK_01 13 2 5V T24 Differential Clock Output for ADC Channel 3 and 4 SCK_01 13 2 5V T25 SCKOUT_01 13 2 5V...

Page 50: ...and 10 SCK_04 12 2 5V V26 SCKOUT_04 15 2 5V F17 Differential Clock Input for ADC Channel 9 and 10 SCKOUT_04 15 2 5V E17 SDO1_04 15 2 5V C17 Differential Data from ADC Channel 9 SDO1_04 15 2 5V C18 SDO...

Page 51: ...d 16 SCK_07 13 2 5V U20 SCKOUT_07 13 2 5V R22 Differential Clock Input for ADC Channel 15 and 16 SCKOUT_07 13 2 5V R23 SDO1_07 12 2 5V AD26 Differential Data from ADC Channel 15 SDO1_07 12 2 5V AE26 S...

Page 52: ...2 5V D18 SDO1_10 15 2 5V A18 Differential Data from ADC Channel 21 SDO1_10 15 2 5V A19 SDO2_10 15 2 5V C16 Differential Data from ADC Channel 22 SDO2_10 15 2 5V B16 CNV_N_10 13 2 5V L24 Convert Signal...

Page 53: ...A conversion is triggered by a negative edge on the CNV line The acquisition is done during the positive phase of the CNV signal Following the FPGA drives the SCK clock which then initiates the data t...

Page 54: ...Input 2 does not need due to the 1 35V VCCO bank I O supply an internal termination The both other LVDS Inputs need an FPGA internal termination The corresponding constrains for the pin assignment th...

Page 55: ...ion FPGA The Configuration I2C Interface provides only one readable register The Serial Number Register is a 32 bit wide read only register The Slave Address of the Serial Number Register is 0b0110101...

Page 56: ...art condition followed by a 7 bit slave address The read write bit in the device address byte is set to one The configuration FPGA acknowledged the address and began to transmit all four data byte of...

Page 57: ...ion on INIT state is active 3 User DONE Green off Device is not configured User FPGA Kintex 7 DONE Pin LED Indicates successful FPGA configuration on Device is completely configured 4 BCC DONE Green o...

Page 58: ...odied so large that it covers a lot of the module Figure 7 15 TXMC638 with Heatsink The actual achievable ambient operating temperature range is highly dependent on the FPGA design the load of the mod...

Page 59: ...ts The example design covers the main functionalities of the TXMC638 It implements a PCIe endpoint with interrupt support register mapping DDR3 memory access and basic I O functions It comes as a Xili...

Page 60: ...out the input voltage range of a differential input one has to differentiate between the differential input voltage between the two pins and the input voltage relative to ground for each pin With an i...

Page 61: ...ntial input can range from 5V to 5V but contains no information about the allowed voltage relative to ground for each input pin If e g VIN 98V and VIN 102V the differential input voltage would be 4V B...

Page 62: ...nput trigger input or simple digital input Differential Source with Ground Reference Vin DIFF_INx FIN1101 COM 3 3V DIFF_INx VIN 100R User FPGA Kintex 7 Termination VIN 200mV up to 3 6V 9 1 3 Back I O...

Page 63: ...AG interface and two TXMC638 status signals The JTAG interface consists of the signals TDI TDO TMS TCK uses 3 3V I O voltage and can run with up to 10 MHz The first status signal indicates the state o...

Page 64: ...TXMC638 User Manual Issue 1 0 2 Page 64 of 86 10 Pin Assignment I O Connector Overview 10 1...

Page 65: ...IN14 11 ADC_IN2 12 ADC_IN14 13 GND 14 GND 15 ADC_IN3 16 ADC_IN15 17 ADC_IN3 18 ADC_IN15 19 GND 20 GND 21 ADC_IN4 22 ADC_IN16 23 ADC_IN4 24 ADC_IN16 25 GND 26 GND 27 ADC_IN5 28 ADC_IN17 29 ADC_IN5 30 A...

Page 66: ...70 ADC_IN24 71 ADC_IN12 72 ADC_IN24 73 GND 74 GND 75 n c 76 n c 77 n c 78 n c 79 GND 80 GND 81 n c 82 DIFF_IN2 83 n c 84 DIFF_IN2 85 GND 86 GND 87 n c 88 DIFF_IN1 89 n c 90 DIFF_IN1 91 GND 92 GND 93 n...

Page 67: ...K_IO18 6 BACK_IO2 38 BACK_IO18 7 BACK_IO3 39 BACK_IO19 8 BACK_IO3 40 BACK_IO19 9 BACK_IO4 41 BACK_IO20 10 BACK_IO4 42 BACK_IO20 11 BACK_IO5 43 BACK_IO21 12 BACK_IO5 44 BACK_IO21 13 BACK_IO6 45 BACK_IO...

Page 68: ...1 0 2 Page 68 of 86 Pin differential I O Pin differential I O 29 BACK_IO14 61 BACK_IO30 30 BACK_IO14 62 BACK_IO30 31 BACK_IO15 63 BACK_IO31 32 BACK_IO15 64 BACK_IO31 Figure 10 1 Pin Assignment P14 Ba...

Page 69: ...10 4 2 Pin Assignment A B C D E F 1 Tx 0 Tx 0 Tx 1 Tx 1 2 GND GND GND GND 3 Tx 2 Tx 2 Tx 3 Tx 3 4 GND GND GND GND 5 6 GND GND GND GND 7 8 GND GND GND GND 9 Reserved Reserved Reserved Reserved 10 GND...

Page 70: ...rect usage of Xilinx software tools like Vivado Logic Analyzer or the Vivado Hardware Manager 10 5 1 Connector Type Pin Count 10 Connector Type JST XRS 10pol 0 6 mm Pitch IDC Connector Source Order In...

Page 71: ...adc_bclk_x to 105MHz clock domain USER_CLKA Version 5 SE 04 07 2016 Removed SPI falling edge alignment to improve SPI timing to allow SelectMAP configuration Version 6 SE 11 07 2016 Added dual purpose...

Page 72: ...set_property LOC GTXE2_CHANNEL_X0Y7 get_cells B_PCIe_FW_UNIT I_PCIe_FW_UNIT B_PCIE_EP I_PCIE_EP U0 inst gt_top_i pipe_wrapper_i pipe_lane 0 gt_wrapper_i gtx_c hannel gtxe2_channel_i set_property PACKA...

Page 73: ...TL135_T_DCI get_ports DQ 9 set_property PACKAGE_PIN AC14 get_ports DQ 9 set_property SLEW FAST get_ports DQ 10 set_property IOSTANDARD SSTL135_T_DCI get_ports DQ 10 set_property PACKAGE_PIN AD14 get_p...

Page 74: ...DQ 29 set_property PACKAGE_PIN AB2 get_ports DQ 29 set_property SLEW FAST get_ports DQ 30 set_property IOSTANDARD SSTL135_T_DCI get_ports DQ 30 set_property PACKAGE_PIN AC2 get_ports DQ 30 set_proper...

Page 75: ...ts BA 1 set_property SLEW FAST get_ports BA 2 set_property IOSTANDARD SSTL135 get_ports BA 2 set_property PACKAGE_PIN AD8 get_ports BA 2 DDR3 Row Address Strobe RAS set_property SLEW FAST get_ports RA...

Page 76: ...AGE_PIN W6 get_ports DQS_P 2 set_property SLEW FAST get_ports DQS_N 2 set_property IOSTANDARD DIFF_SSTL135_T_DCI get_ports DQS_N 2 set_property PACKAGE_PIN W5 get_ports DQS_N 2 set_property SLEW FAST...

Page 77: ...property IOSTANDARD LVDS_25 get_ports ADC_SDO2_P 0 set_property DIFF_TERM TRUE get_ports ADC_SDO2_P 0 set_property PACKAGE_PIN AD25 get_ports ADC_SDO2_P 0 set_property SLEW FAST get_ports ADC_SDO2_N 0...

Page 78: ...tapath_only from adc_bclk_1 to USER_CLKA set_max_delay 10 datapath_only from USER_CLKA to adc_bclk_1 ADC 2 set_property SLEW FAST get_ports ADC_CNV_n 2 set_property IOSTANDARD LVCMOS25 get_ports ADC_C...

Page 79: ...y IOSTANDARD LVDS_25 get_ports ADC_SDO1_P 3 set_property DIFF_TERM TRUE get_ports ADC_SDO1_P 3 set_property PACKAGE_PIN H16 get_ports ADC_SDO1_P 3 set_property SLEW FAST get_ports ADC_SDO1_N 3 set_pro...

Page 80: ...k_4 min 0 get_ports ADC_SDO1_P 4 set_input_delay clock adc_bclk_4 max 2 get_ports ADC_SDO2_P 4 set_input_delay clock adc_bclk_4 min 0 get_ports ADC_SDO1_P 4 set_input_delay clock adc_bclk_4 max 2 get_...

Page 81: ...perty PACKAGE_PIN AA23 get_ports ADC_SCKOUT_P 6 set_property IOSTANDARD LVDS_25 get_ports ADC_SCKOUT_N 6 set_property DIFF_TERM TRUE get_ports ADC_SCKOUT_N 6 set_property PACKAGE_PIN AB24 get_ports AD...

Page 82: ...LVDS_25 get_ports ADC_SDO2_N 7 set_property DIFF_TERM TRUE get_ports ADC_SDO2_N 7 set_property PACKAGE_PIN N24 get_ports ADC_SDO2_N 7 Timings create_clock name adc_bclk_7 period 9 5238095238095238095...

Page 83: ...N AA25 get_ports ADC_SCK_P 9 set_property IOSTANDARD LVDS_25 get_ports ADC_SCK_N 9 External Termination set_property PACKAGE_PIN AB25 get_ports ADC_SCK_N 9 set_property IOSTANDARD LVDS_25 get_ports AD...

Page 84: ...s ADC_SDO2_P 10 set_property IOSTANDARD LVDS_25 get_ports ADC_SDO2_P 10 set_property DIFF_TERM TRUE get_ports ADC_SDO2_P 10 set_property PACKAGE_PIN C16 get_ports ADC_SDO2_P 10 set_property SLEW FAST...

Page 85: ...get_ports ADC_SDO2_P 11 set_clock_groups asynchronous group adc_bclk_11 group USER_CLKA set_max_delay 10 datapath_only from adc_bclk_11 to USER_CLKA set_max_delay 10 datapath_only from USER_CLKA to a...

Page 86: ...get_ports USER_LED 0 set_property IOSTANDARD LVCMOS33 get_ports USER_LED 0 set_property PACKAGE_PIN J26 get_ports USER_LED 0 set_property SLEW FAST get_ports USER_LED 1 set_property IOSTANDARD LVCMOS...

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