Tews Technologies TXMC638, User Manual

Page: 37 / 86

TXMC638 User Manual Issue 1.0.2 Page 37 of 86
The following table lists the available clock sources on the TXMC638:
FPGA Clock-Pin Name FPGA Pin
Number
Source Description
MGTREFCLK0_115 H6 / H5 SI5338 low-jitter clock
generator 156.25 MHz differential
MGT Reference clock
MGTREFCLK0_116 D6 / D5 PCIe Switch
PI7C9X2G312GP 100 MHz differential
PCIe Reference clock input
IO_L13P/N_T2_MRCC_33 AB11 / AC11 SI5338 low-jitter clock
generator 88.889 MHz differential MCB
CLK
IO_L14P/N_T2_SRCC_33 AA10 / AB10 SI5338 low-jitter clock
generator 200 MHz differential Reference
clock
IO_L12P_T1_MRCC_14 F22 SI5338 low-jitter clock
generator 105 MHz Clock Input
This clock is designated for
ADC interface clock source.
IO_L13P/N_T2_MRCC_14 G22 / F23 Si514 prog. Oscillator Differential free I2C prog. XO
100kHz up to 250MHz
Default = 156 MHz
IO_L12P/N_T1_MRCC_12 Y23 / AA24 LTC2323 Diff. Clock ADC Ch. 1 and 2
IO_L13P/N_T2_MRCC_13 R21 / P21 LTC2323 Diff. Clock ADC Ch. 3 and 4
IO_L14P/N_T2_SRCC_12 AC23 / AC24 LTC2323 Diff. Clock ADC Ch. 5 and 6
IO_L14P/N_T2_SRCC_15 H17 / H18 LTC2323 Diff. Clock ADC Ch. 7 and 8
IO_L12P/N_T1_MRCC_15 F17 / E17 LTC2323 Diff. Clock ADC Ch. 9 and 10
IO_L12P/N_T1_MRCC_13 N21 / N22 LTC2323 Diff. Clock ADC Ch. 11 and 12
IO_L11P/N_T1_SRCC_12 AA23 / AB24 LTC2323 Diff. Clock ADC Ch. 13 and 14
IO_L14P/N_T2_SRCC_13 R22 / R23 LTC2323 Diff. Clock ADC Ch. 15 and 16
IO_L13P/N_T2_MRCC_12 Y22 / AA22 LTC2323 Diff. Clock ADC Ch. 17 and 18
IO_L11P/N_T1_SRCC_15 G17 / F18 LTC2323 Diff. Clock ADC Ch. 19 and 20
IO_L13P/N_T2_MRCC_15 E18 / D18 LTC2323 Diff. Clock ADC Ch. 21 and 22
IO_L11P/N_T1_SRCC_13 P23 / N23 LTC2323 Diff. Clock ADC Ch. 23 and 24
IO_L13P/N_T2_MRCC_16 C12 / C11 Back I/O Connector Diff. P14 Back I/O Clock Input
IO_L14P/N_T2_SRCC_16 E11 / D11 Back I/O Connector Diff. P14 Back I/O Clock Input
IO_L12P/N_T1_MRCC_16 E10 / D10 Back I/O Connector Diff. P14 Back I/O Clock Input
IO_L11P/N_T1_SRCC_16 G11 / F10 Back I/O Connector Diff. P14 Back I/O Clock Input
IO_L3N_T0_DQS_EMCCLK_
14 B26 BCC 53.2 MHz used for external
configuration clock (CCLK)
Table 7-5 : Available FPGA clocks