TXMC638 User Manual Issue 1.0.2
Page 20 of 86
5.2.7 ISP Command Register - 0xE8
Bit
Symbol
Description
Access
Reset
Value
31:2
Reserved
-
0
1
ISP_SPI_RST_CMD
ISP SPI Reset Command Bit
Writing a ‘1’ sets the Instruction Busy Bit in the
ISP Status Register (if not already set).
Breaks any ISP SPI instruction in progress and
resets the ISP SPI logic.
Check the Instruction Busy Bit in the ISP Status
Register for reset done status.
Always read as ‘0’.
R/W
0
0
ISP_SPI_INS_CMD
ISP SPI Start Instruction Command Bit
Writing a ‘1’ sets the SPI Instruction Busy Bit in
the ISP Status Register and starts the configured
SPI instruction.
Ignored (lost) while the Instruction Busy Bit is set
in the ISP Status Register.
Always read as ‘0’.
R/W
0
Table 5-7 : ISP Command Register
5.2.8 ISP Status Register - 0xEC
Bit
Symbol
Description
Access
Reset
Value
31:2
Reserved
-
0x00_0000
1
ISP_SPI_
INS_BSY
ISP SPI Instruction Busy Status
Set & Cleared automatically by HW.
Includes SPI Flash internal program/erase times.
When clear again after being set, a new ISP SPI
instruction may be started.
Capable of generating an event based interrupt.
0: No ISP SPI Instruction in Progress
1: ISP SPI Instruction in Progress
R
0
0
ISP_SPI_
DAT_BSY
ISP SPI Data Transfer Busy Status
Set & Cleared automatically by HW.
Does not include SPI Flash internal program/erase
times.
When clear again after being set, new SPI Flash page
data may be written to the ISP Data Space (in program
mode) or SPI Flash page data is available in the ISP
data space (in read mode).
Capable of generating an event based interrupt.
0: No ISP SPI Data Transfer in Progress
1: ISP SPI Data Transfer in Progress
R
0
Table 5-8 : ISP Status Register
