TXMC638 User Manual Issue 1.0.2
Page 36 of 86
Changing or erase the BCF content leads to an inoperable TXMC638 FPGA configuration.
Clocking
7.6
7.6.1 FPGA Clock Sources
As a central clock generator of TXMC638 the Si5338 clock generator is used. This provides all necessary
clocks for the User FPGA and the Configuration FPGA.
The following figure depicts an abstract User FPGA clock flow.
Si514
prog. XO
Si5338 Clock Generator
BCC
Kintex-7
DDR3
PCIe Switch
Bank
33
32MHz
Oscillator
200
M
H
z
R
EF
_C
LK
88
.8
89
M
H
z M
C
B_
C
LK
156.
25
M
H
z
100M
H
z
PCIe
to
PCI
25 MHz
PCI-CLK
100 MHz
User definied
open
100 MHz
DDR3 Memory Clocks
MGT Ref. Clocks
EM
CCL
K
SPI
CCL
K
2 - 133
MHz
internal
DIV
EN
Config Clocks
open
P14
12 x
Dual-ADC
12 x
CLK_IN
ADC Clocks
Bank 115
Bank 12, 13, 15
Bank 16
Bank 116
Bank 14
CL
K_
M
G
T
105
M
H
z
4 x CLK
156
M
H
z
De
fa
ul
t
12
x
C
LK
_O
U
T
P15
53.2 MHz
Figure 7-5 : FPGA Clock Sources
