TXMC638 User Manual Issue 1.0.2
Page 71 of 86
11 Appendix A
This appendix contains the signal to pin assignments for the User FPGA Kintex-7.
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## TEWS TECHNOLOGIES ##
## ############################################################################################# ##
##
## Project Name : TXMC638 Example
## File Name
: txmc638_exa.xdc
## Target Device : XC7K160T-FBG676-1
## Design Tool : Xilinx Vivado Design Suite Design Edition 2015.3
## Simulation Tool :
##
## Description : Constraint file TXMC638 FPGA/K7 Firmware
##
## Owner : TEWS TECHNOLOGIES GmbH
## Am Bahnhof 7
## D-25469 Halstenbek
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## Tel.: +49 / (0)4101 / 4058-0
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Fax.: +49 / (0)4101 / 4058-19
## e-mail: [email protected]
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## Copyright (c) 2016
## TEWS TECHNOLOGIES GmbH
##
## History :
## Version 1 : (SE, 07.06.2016)
##
Initial Version
## Version 2 : (SE, 15.06.2016)
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- Added master SPI x4 configuration mode
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- Added clock constraints for ADC bit clocks (adc_clkout_x)
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- Added timing constraints for ADC data inputs (adc_sdo1/2_x)
## Version 3 : (SE, 17.06.2016)
##
- Added external master clock usage w/o divider
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- Added differential termination for ADC data inputs (adc_sdo1/2_x)
## Version 4 : (SE, 24.06.2016)
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- Set SPI falling edge alignment (to improve SPI timing)
## - Set asynchronous clock group constraints for ADC bit clock (adc_bclk_x) to 105MHz clock
domain (USER_CLKA)
##
Version 5 : (SE, 04.07.2016)
##
- Removed SPI falling edge alignment (to improve SPI timing) to allow SelectMAP
configuration
## Version 6 : (SE, 11.07.2016)
## - Added dual purpose I/O persistence (BITSTREAM.CONFIG.PERSIST) and configuration mode
(CONFIG_MODE)
## - Added data path timing constraints for ADC bit clock (adc_bclk_x) from/to 105MHz clock
domain (USER_CLKA)
## Version 7 : (SE, 24.08.2016)
##
- Changed I/O locations due to new PCB version (CNV_3/4/9/10, DIFF_K7_0/1,
SCK_0/3/4/8/9/10, SCKOUT_0, SDO1_7/11, SDO2_0/2/5)
##
- Changed iostandard for I/Os DIFF_K7_0/1 incl. internal termination (DIFF_TERM TRUE)
## Version 8 : (SE, 26.08.2016)
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- Added SPI falling edge constraint (SPI_FALL_EDGE)
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- Added bitstream compression (COMPRESS)
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## Comments : none#
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## Section: Miscellaneous
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# Bitstream Setting
set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN div-1 [current_design]
set_property BITSTREAM.CONFIG.PERSIST YES [current_design]
set_property CONFIG_MODE SPIx4 [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
#SE, 28.08.2016: Falling edge setting is required for direct used external master clock (EXTMASTERCCLK_EN div-1)
set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]
set_property BITSTREAM.GENERAL.COMPRESS true [current_design]
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## Section: MGT
