TXMC638 User Manual Issue 1.0.2
Page 16 of 86
5 Register Description
User FPGA (Kintex-7)
5.1
The FPGA register description depends on the user application and is not part of this specification.
Board Configuration Controller (BCC - FPGA)
5.2
5.2.1 Interrupt Enable Register - 0xC0
Bit
Symbol
Description
Access
Reset
Value
31:2
Reserved
0
1
ISP_INS_IE
ISP SPI Instruction Done Event Interrupt Enable
0: Interrupt Disabled
1: Interrupt Enabled
While disabled, the corresponding bit in the Interrupt
Status Register is ‘0’.
Disabling interrupts does not affect the interrupt
source.
R/W
0
0
ISP_DAT_IE
ISP SPI Page Data Request Event Interrupt Enable
0: Interrupt Disabled
1: Interrupt Enabled
While disabled, the corresponding bit in the Interrupt
Status Register is ‘0’.
Disabling interrupts does not affect the interrupt
source.
R/W
0
Table 5-1 : Interrupt Enable Register
5.2.2 Interrupt Status Register - 0xC4
Bit
Symbol
Description
Access
Reset
Value
31:2
Reserved
0
1
ISP_INS_IS
ISP SPI Instruction Done Event Interrupt Status
When set, the PCI INTA# interrupt is asserted.
The Interrupt is cleared by writing a ‘1’.
0: Interrupt not active or disabled
1: Interrupt active and enabled
R/C
0
0
ISP_DAT_IS
ISP SPI Page Data Done Event Interrupt Status
When set, the PCI INTA# interrupt is asserted.
The Interrupt is cleared by writing a ‘1’.
0: Interrupt not active or disabled
1: Interrupt active and enabled
R/C
0
Table 5-2 : Interrupt Status Register
