Remote Control
MTD200 MPEG Test Decoder User Manual
5–53
Status Byte (STB) and Service Request Enable Register (SRE).
The Status Byte
Register is defined in IEEE 488.2. It is the root of the SCPI status register tree.
The previously defined bits of the IEEE 488.2 standard have remained un-
changed. Bits 3 and 7 are new. These are the summary bits of the QUEStionable
and OPERationable status registers. Although the STB is integrated into the
SCPI hierarchy, there are some historical differences.
The function of the Service Request Enable Register SRE corresponds to that of
the ENABle register of STB. The summary bit of the STB is its own bit 6. The
STB has no EVENt register; it directly represents the device status in the
CONDition register.
PTRansition and NTRansition registers have no significance and are not defined.
Each bit of the STB is assigned a bit in the SRE. Bit 6 of the SRE is ignored. If a
bit is set in the SRE and the associated bit in the STB changes from 0 to 1, a
Service Request (SRQ) will be generated which triggers an interrupt in the
controller, provided that the controller has been configured accordingly and can
be further processed by the controller.
The Status Byte Register is read out by the query *STB?. The SRE can be set by
the command *SRE and read out by the query *SRE?.
Table 5–7: Definition of bits in the Status Byte Register
Bit No.
Definition
ÁÁÁÁ
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
ÁÁÁÁ
2
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Error Queue not empty
This bit is set when the Error Queue receives an entry.
If this bit is enabled by the SRE, each entry of the Error Queue will generate a
Service Request. An error can thus be recognized and specified in detail by
querying the Error Queue.
The query returns a conclusive error message.
ÁÁÁÁ
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
ÁÁÁÁ
3
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
QUEStionable Status summary bit
This bit is set if in the QUEStionable Status Register an EVENt bit is set and the
associated ENABle bit is set to 1.
A set bit denotes a questionable device status which can be specified in greater
detail by querying the QUEStionable Status Register.
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
4
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
MAV bit (Message available)
This bit is set if a readable message is in the output buffer.
Description of Status
Registers
Summary of Contents for MTD200
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