Tektronix 422, Instruction Manual

Page: 43 / 213

Circuit Description—Type 422 AC-DC
In the .01 position, R30 provides the emitter resistance
fo r Q34 and the gain o f the stage is five. In the .02 position,
R32 provides the emitter resistance fo r Q34 to result in a
stage gain of 2.5. In the .05 and higher Channel 1
VO LTS /D IV switch positions, the emitter Resistance is
in fin ity (open circuit) to produce a gain fo r this stage of
one. As mentioned in the Input Stage discussion, the STEP
A T T BAL adjustment is set to provide a zero-volt level at
the em itter o f Q34 under quiescent conditions. Since there
is no voltage difference across the em itter resistance of
Q34, changing the emitter resistance does not change the
current in the circuit. Therefore, the trace position does not
change when switching between the .01, .02 and .05
positions o f the Channel 1 VO LTS/D IV switch.
Zener diode D41 along with the network C41-R41 pro­
vides a stable, low-impedance voltage source fo r the emitter
of Q44. Diode D30 protects the base-emitter junction o f
Q44 against reverse breakdown from high negative input
voltages. Capacitor C40 provides high-frequency regenera­
tive feedback from the collector to base o f Q44 to stabilize
this stage. Variable Balance adjustment R35 sets the output
DC level of the Feedback A m plifier stage so there is no
current flo w between the emitters o f Q84 and Q94 in the
Paraphase A m plifier stage under quiescent conditions. With
this configuration, the position of the zero-volt reference
trace w ill not shift as the Channel 1 V A R IA B LE control is
rotated.
Channel 1 Trigger P icko ff
The signal at the collector of Q44 in the Feedback
A m p lifie r stage is connected to the Channel 1 Trigger Pick­
o ff stage through R51. This sample o f the Channel 1 input
signal provides internal triggering from the Channel 1 signal
only. Q53 is connected as an emitter follow er to provide
isolation between the Channel 1 Input A m p lifie r and the
Sweep Trigger circuits. It also provides a minimum load fo r
the Feedback A m plifier stage and a low output impedance
to the Sweep Trigger circuit. The CH 1 Trigger DC Level
adjustment R57 provides a zero-volt DC output level to the
Sweep Trigger circuit with no signal applied to Channel 1.
O utput from the Channel 1 Trigger Pickoff stage is connec­
ted to the Sweep Trigger circuit through the TRIGGERING
Source switch.
Paraphase A m p lifie r
The output signal from the Feedback A m p lifie r stage is
connected to the Paraphase A m p lifie r stage. Q84 and Q94
are connected as a common-emitter phase inverter (par­
aphase am plifer)2 to convert the single-ended input signal
to a push-pull output signal. Gain o f this stage is deter­
mined by emitter degeneration. As the resistance between
the emitters of Q84 and Q94 increases, emitter degenera­
tion increases also, to result in less gain through the stage.
GAIN adjustment R80 varies the resistance between the
emitters o f Q84 and Q94 to set the overall gain o f the
Channel 1 Input Am plifier. This control is set to provide
calibrated vertical deflection factors. Channel 1 V A R I­
ABLE control R90 provides variable gain to provide con­
tinuously variable deflection factors between the calibrated
settings o f the Channel 1 V O LTS/D IV switch. The network
C78-D78-R77-R78-R79 connected to the base o f Q94 pro­
vides the same DC level and circuit response in the Channel
1 Input A m plifier as the X9 Gain Stage provides in the
Channel 2 Input A m p lifie r circuit. Vertical position o f the
trace is determined by Channel 1 POSITION control R60.
This control sets the conduction o f Q64 and Q74, which
controls the quiescent emitter current o f Q84 and Q94. The
output signal at the collectors o f Q84 and Q94 is connected
to the Diode Gate stage in the Vertical Switching and O ut­
p u t A m p lif ie r c ir c u it th ro u g h C84-R84-R85 and
C94-R94-R95.
CHANNEL 2
INPUT A M P L IF IE R
General
The Channel 2 Input A m p lifie r circuit is basically the
same as the Channel 1 Input A m p lifie r circuit. Only the
differences between the tw o circuits are described here.
Portions of this circuit not described in the following
discussion operate in the same manner as fo r the Channel 1
Input A m plifier circuit (corresponding circuit numbers
assigned in the 100 - 199 range). Fig. 3-3 shows a detailed
block diagram of the Channel 2 Input A m plifier circuit. A
schematic o f this circuit is shown on diagram 2 at the back
o f the manual.
Feedback Amplifier
Basically, the Channel 2 Feedback A m plifier stage op­
erates as described fo r Channel 1. Flowever, there are
several differences. Channel 2 does not have a trigger pick­
o ff circuit. C l43 and R143 provide a similar load at the
collector of Q144 to that provided by the Channel 1 Trig­
ger Pickoff stage at the collector o f Q44. This RC network
assures similar response in each channel. Also, Channel 2
has a X 10 gain feature which is not contained in Channel 1.
Complete operation o f this feature is described under X9
Gain Stage.
X9 Gain Stage
The Channel 2 Input A m plifier circuit contains an addi­
tional amplifier stage comprised o f Q154 and its associated
components. The signal at the collector of Q144 in the
Channel 2 Feedback A m p lifie r stage is connected to the
X I 0 GAIN AC switch SW150. When this switch is in the X I
position (pushed in), the X9 Gain Stage establishes the DC
level at the base o f Q194. The Channel 2 Paraphase A m p li­
fier stage operates in the same manner as described fo r
Channel 1. When the X10 GAIN AC switch is pulled out to
the X I 0 position, the signal from the Channel 2 Feedback
A m plifier stage is capacitively coupled to the X9 Gain Stage
as well as to the Channel 2 Paraphase A m plifier stage. Am p­
lifier Q154 provides nine times gain fo r the signal which is
connected to its base through R151 and C151. This ampli­
fied signal is connected to the base o f Q194 in the Channel
2 Paraphase A m p lifie r stage through R156. Normal gain o f
the Paraphase A m p lifie r is one times. The amplified signal
2Lloyd P. Hunter (ed.), “Handbook of Semiconductor Electronics”,
second edition, McGraw-Hill, New York, pp. 11-94.
E ll
3-5