Theory of Operation
1735 HD High Definition Waveform Monitor
4–13
Table 4–1: Control signals grouped by function (Cont.)
Block diagram
Corresponding schematic
diagram signal names
Circuit block
Corresponding schematic
diagram signal names
Control signal
FRONT PANEL
SWITCHES
ROW0
ROW1
ROW2
ROW3
COL0
COL1
COL2
COL3
FRONT PANEL
LIGHTS
DIGIT1
DIGIT2
DIGIT3
DIGIT4
S0
S1
S2
S3
S4
S5
Master Processor.
The master processor consists of U33 and U32. U32 is the
erasable-programmable read-only memory (EPROM) containing the instruction
code for the microprocessor, U33. Port 0 of U33 is used for multiplexed address
and data lines. U31 is a tri-state octal D-Type latch which determines the address
lines. The front-panel switch matrix is read directly by U33 through Port 1 which
provides a stimulus via ROW 0–3, and evaluates the response through COL 0–3.
Microcontroller
Diagram <8>
Summary of Contents for 070-8462-03
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Page 13: ...Table of Contents viii 1735 HD High Definition Waveform Monitor...
Page 19: ...Preface xiv 1735 HD High Definition Waveform Monitor...
Page 20: ...Getting Started...
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Page 35: ...Installation 1 14 1735 HD High Definition Waveform Monitor...
Page 36: ...Operating Basics...
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Page 64: ...Specifications...
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Page 78: ...Theory of Operation...
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Page 110: ...Performance Verification...
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Page 179: ...Corrective Maintenance 7 20 1735 HD High Definition Waveform Monitor...
Page 181: ...Repackaging 7 22 1735 HD High Definition Waveform Monitor Figure 7 10 Repackaging...
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