Theory of Operation
4–8
1735 HD High Definition Waveform Monitor
Filter Select.
When no filter is selected (FLAT), full bandwidth video passes
through U10 to the gain cell in U25; U15 and U9 are disabled. When the NOISE
filter is selected, filtered video passes through U15 to the gain cell in U25; U10
and U9 are disabled. When the DIFF STEP filter is selected, filtered video
passes through U9 to U25.
Vertical Limiter and Vertical Deflection.
The vertical limiter, gain cell, and vertical
level shift are in U25 (a Tektronix ASIC). The inverted 2X video from the filter
switch is attenuated to 1X video by R64 and R137 at U25 pin 9. Analog control
signals VSIZE and VMOVE control the gain cell and vertical level shift. The
vertical limiter clips portions of the video that would be far off screen, reducing
the dynamic range needed in the vertical deflection amplifier. This limit
corresponds to approximately 2 V differential between U25, pins 29 and 33. The
control signal VERT5X selects five times gain at the limiter (in U25).
The vertical deflection amplifier is a differential cascode stage driven by U25.
The resistors at U25, pins 29 and 33 determine the operating current and current
gain at U25, pins 30 and 31. This current is converted back to a voltage gain by
resistors at the collectors of Q26 and Q34. T-coil peaking (L8 and L9) at the
output to the deflection plates improves the bandwidth. The voltage output at the
collector of each cascode (Q26 and Q34) is approximately 19 V at the center of
the screen, 19 V
±
6 V at a graticule edge, or 19 V
±
10 V at a limit. Transistors
Q24 and Q33 hold –0.7 V at U25 pins 30 and 31, and dissipate power that is not
needed by the output cascode.
When readout is active, the vertical deflection amplifier input is disconnected
from the video at the limiter output and switched to the readout amplifier
(internal to U25, controlled by ROEN). U24 scales and shifts the vertical readout
signal (ROVERT) for U25.
Vertical Output
Diagram <5>
Summary of Contents for 070-8462-03
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