Tektronix 070-8462-03, Instruction Manual

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Theory of Operation
1735 HD High Definition Waveform Monitor
4–9
Sweep Generator.
The sweep generator is controlled by the microcontroller.
Sweep and retrace are directly enabled and disabled by the control line
/SWPGATE, which is high for retrace and low for sweep. If Q16 is off, the
sweep ramps up at a rate determined by the current from the DAC (U17) and the
timing capacitor (C63 for line rate sweeps or C63 with C62 in parallel for field
rate sweeps).
Line rate ramps are generated by an integrator consisting of amplifier U26A,
timing capacitor C63, and a programmable current from the DAC, along with a
current mirror consisting of Q10, Q9, Q14, & Q15.
To generate a field-rate ramp, C62 is added in parallel with C63 by turning on
Q8. The output of U26A is a positive ramp of approximately 4 V or 8 V,
depending upon the selection (either 1 line, field or 2 line, field). The DAC’s
data inputs are latched from U14, which is a serial-to-parallel shift register. The
data input to U14 comes directly from the microprocessor (Diagram 8).
Horizontal Level Shift. The front-panel HORIZONTAL position control setting is
fed to the Main board through the Control board. The position voltage is input to
pin 2 of U23A, which buffers the positioning voltage. This voltage is summed at
the input of the horizontal mag amplifier. During sweep (no readout), Q11 is
saturated and U26B operates as a conventional inverting amplifier. During
readout, the horizontal positioning voltage from U23A is applied to inverting
and non-inverting inputs to U26B so that the position control does not affect the
readout. U23B is a comparator with its output (pin 7) high for sweep and low for
readout.
Horizontal Diagram <6>