Tektronix 070-8462-03, Instruction Manual

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Theory of Operation
1735 HD High Definition Waveform Monitor
4–21
Sweep Gate. U15B NORs REM_SYNC with HSYNC, and outputs the clock
signal for U12, U13A, and U14.
U13A is a J-K flip-flop enabled by the slave microprocessor. Its output is a
single negative-going pulse. When either H SYNC or /ONELINE goes high,
U15C has a low output that is inverted by U10A to satisfy one input to the
/SWPGATE generator.
U14 is an 8-input D-type flip-flop that is cleared by /ROEN. It latches through
slave microprocessor-generated signals VERT5X, FILTER0, FILTER1, /STRB,
LINBLANK, LINSTEP, and the line sweep enable. The line sweep enable
(LINSWPEN) is one of the signals used to generate the sweep gate. Clearing
U14 during readout with /ROEN disables all functions that affect the display,
such as vertical magnification or filters. This ensures that the readout always
appears properly.
The sweep gate generator, U10B, is a 2-input NAND gate, ANDing HSYNC and
LINE SWEEP ENABLE to generate the /SWPGATE used by the horizontal
timing circuits (Main circuit board).
During line-rate sweeps, the slave microprocessor sets U14 pin 16 high and
U13A gates through Hsync pulses to U10B at the selected period (two line or
three line). During field rate sweeps, the slave microprocessor uses U13A to set
U10A, pin 3 high. U14, pin 15 then directly controls sweep gating, through
U10B.
U12 is an 8-input D-Type flip-flop used as a latch for the slave microprocessor
video input channel select and offset select control signals.