Supero SUPER P6SLA, User'S And Bios Manual

Page: 64 / 91

Chapter 5: Running Setup
5-9
SDRAM Timing Latency
Use this feature to select the SDRAM timing delay. The settings
for thi s option are
Manual or Auto.
SDRAM RAS to CAS
The settings for this option are 3 Clks or 2 Clks.
SDRAM CAS Lat
This feature is for the Column Address Strobe latency. The
settings for this option are 3 Clks or 2 Clks.
SDRAM RAS Precharge
This feature is for the SDRAM Row Address Strobe delay. The
settings for this option are 3 Clks or 2 Clks.
VGA Frame Buffer USWC
USWC is a memory cycle type that stands for Uncacheable
Speculative Write Combining. The settings are: Disabled or
Enabled.
PCI Frame Buffer USWC
The settings for this option are: Disabled or Enabled. When
Enabled, the PCI frame buffer address and length are divided into
2. The value is then programmed into the processor Variable
MTRR (3) with the value for USWC (01h).
DRAM Integrity Mode (ECC)
The settings for this option are: Non ECC, EC only or ECC. Set
this option to Enabled to enable ECC DRAM integrity mode. ECC
allows critical system to detect and correct memory errors, while
normal parity generator/checker can only detect such memory
errors.
Fixed Memory Hole
This option allows a memory hole to be specified for either the
512-640K region or the 15-16M region. The settings for this
option are Disabled, 512-640KB or 15-16MB.