2-15
BVW-55
IC
CXB1341R (SONY)
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
V
CCL
GND
V
CCL
NC
V
CCL
NC
NC
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CCT
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
V
CCT
V
CCL
GND
GND
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
V
CC
V
CCS
GND
GND
V
CC2
GND
SERIAL DIGITAL INTERFACE TRANSMISSION ENCODER
—TOP VIEW—
GND
V
CCL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
—
I
I
I
I
I
I
I
I
I
I
—
—
—
—
—
V
CCL
D1X
D1Y
D0X
D0Y
PCX
PCY
SCKX
SCKY
TEST
RESET
V
CCT
V
CCL
GND
GND
NC
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
—
—
—
I
—
I
—
I
—
O
O
—
I
I
I
I
NC
NC
V
CCL
MDS
NC
BCAP
V
CCL
ICP
GND
CPX
CPY
V
CCL
FSR0
FSR1
FSR2
FSR3
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
—
I
I
—
O
I
—
—
O
—
O
—
I
O
I
I
GND
MOD0
MOD1
V
CC2
LST
THRU
GND
GND
SX
V
CCS
SY
V
CCL
ETS
PCK
D9X
D9Y
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
—
I
I
I
I
I
I
I
I
I
I
I
I
I
I
—
V
CCT
D8X
D8Y
D7X
D7Y
D6X
D6Y
D5X
D5Y
D4X
D4Y
D3X
D3Y
D2X
D2Y
GND
PIN
NO.
I/O
SIGNAL
PIN
NO.
I/O
SIGNAL
PIN
NO.
I/O
SIGNAL
PIN
NO.
I/O
SIGNAL
: EXTERNAL CAPACITOR FOR VCO
: POSITIVE PARALLEL DATA
: NEGATIVE PARALLEL DATA
: 8-BIT/10-BIT SELECT (L = 8-BIT, H OR OPEN = 10-BIT)
: EXTERNAL RESISTOR FOR SETTING THE FREE-RUN FREQUENCY OF VCO
: EXTERNAL RESISTOR FOR CHARGE PUMP
: TEST
: VCO RATE SELECT
: POSITIVE PARALLEL CLOCK
: NEGATIVE PARALLEL CLOCK
: PLL RESET
: TEST
: TEST
: TEST
: PLL LOCK STATUS
: PARALLEL CLOCK
: CHARGE PUMP
: EXTERNAL RESISTOR FOR SERIAL DIFFERENTIAL
INPUT
BCAP
D9X - D0X
D9Y - D0Y
ETS
FSR0 - FSR3
ICP
MDS
MOD0, MOD1
PCX
PCY
RESET
SCKX, SCKY
TEST
THRU
OUTPUT
LST
PCK
CPX, CPY
SX, SY
1/10 COUNTER
10-BIT LATCH
10-BIT LATCH
P/S CONVERTER
SCRAMBLER
NRZ-NRZI
SYNC CONV.
47
D9X
48
D9Y
50
D8X
51
D8Y
52
D7X
53
D7Y
54
D6X
55
D6Y
56
D5X
57
D5Y
58
D4X
59
D4Y
60
D3X
61
D3Y
62
D2X
63
D2Y
2
D1X
3
D1Y
4
D0X
5
D0Y
6
PCX
7
PCY
8
SCKX
9
SCKY
10-BIT
10-BIT
SERIAL DATA
8-BIT
PARALLEL CLK
INT. PARALLEL CLK
EXT. PARALLEL CLK
_
90
d
SIFT PSK
_
_
11
RESET
SYNC DET.
LOCK
DET.
RESET
PHASE
COMP.
VCO
FREE RUN SET
1/2
CHARGE
PUMP
8-BIT
2LSBs
2LSBs
PCK
46
SY
43
SX
41
THRU
38
ETS
45
TEST
10
LST
37
MDS
20
MOD1
35
MOD0
34
24
ICP
26
CPX
27
CPY
22
BCAP
29
FSR0
30
FSR1
31
FSR2
32
FSR3
LOAD PULSE
SERIAL CLK
INPUT
CLK
DIN0 - DIN10
DOP
MODE
OEN
TINT
SCK
SIN
STB
YC
DG1-DG3
LTP
CP2
INV
OUTPUT
DOT0 - DOT10
SDO
SOUT
TOT
; CLOCK
; DATA
; DO PULSE
; H : 14CK DELAY
L : 5CK DELAY
; OUTPUT ENABLE
L : DOT0-10 OUTPUT STATUS
H : HIGH IMPEDANCE STATUS
; H : MPU COMMUNICATION MODE
; MPU SERIAL I/F CLOCK
; MPU SERIAL DATA IN
; MPU SERIAL I/F STROBE
; L : CHROMA, H : Y
; FOR DIAG
; FOR DIAG
; TEST TERMINAL GENERALLY USE : L
; TEST TERMINAL GENERALLY USE : L
; DATA
; STRETCHED DO
; DATA OUT TO MPU
; TEST
24
23
22
21
20
19
18
17
16
15
14
13
NC
V
DD
NC
NC
36
35
34
33
32
31
30
29
28
27
26
25
GND
1
2
3
4
5
6
7
8
9
10
11
12
GND
37
38
39
40
41
42
43
44
45
46
47
48
1
2
3
4
5
7
8
9
10
47
48
11
24
25
14
15
16
17
20
21
22
23
12
39
40
42
DOT0
DOT1
DOT2
DOT3
DOT4
DOT5
DOT6
DOT7
DOT8
DOT9
DOT10
SDO
SOUT
TOT
36
35
34
33
32
31
29
28
27
38
37
26
13
46
DIN0
DIN1
DIN2
DIN3
DIN4
DIN5
DIN6
DIN7
DIN8
DIN9
DIN10
DOP
MODE
OEN
SCK
SIN
STB
YC
LTP
DG1
DG2
DG3
TINT
INV
CP2
V
DD
NC
( )
C-MOS DIGITAL DELAY LINE
—TOP VIEW—
CXD101-106Q (SONY)
DOT0
DIN0 - 10
CLK
MODE
DOP
OEN
SCK
SIN
STB
YC
DG1 - 3
20 - 23
LTP
TINT
1 - 5, 7 - 10,
47, 48
42
24
11
25
14
15
16
17
12
4
11
11
9
11
SDO
SOUT
27 - 29,
31 - 38
26
13
1
2
3
4
5
6
7
8
9
10
11
12
I
I
I
I
I
—
I
I
I
I
I
I
DIN0
DIN1
DIN2
DIN3
DIN4
GND
DIN5
DIN6
DIN7
DIN8
DOP
TINT
4 CLOCK
DELAY
14 CLOCK
DELAY
MPU
INTERFACE
9 CLOCK
DELAY
D Q
13
14
15
16
17
18
19
20
21
22
23
24
O
I
I
I
I
—
—
I
I
I
I
I
SOUT
SCK
SIN
STB
YC
NC
V
DD
LTP
DG1
DG2
DG3
MODE
25
26
27
28
29
30
31
32
33
34
35
36
I
O
O
O
O
—
O
O
O
O
O
O
OEN
SDO
DOT8
DOT7
DOT6
GND
DOT5
DOT4
DOT3
DOT2
DOT1
DOT0
37
38
39
40
41
42
43
44
45
46
47
48
PIN
NO.
PIN
NO.
PIN
NO.
PIN
NO.
O
O
I
I
—
I
—
—
—
O
I
I
DOT10
DOT9
INV
CP2
NC
CLK
V
DD
NC
NC
TOT
DIN9
DIN10
I/O
SIGNAL
I/O
SIGNAL
I/O
SIGNAL
I/O
SIGNAL
Summary of Contents for BVW-55
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