U-Boot
ATCA-F140 Series Installation and Use (6806800M67S)
119
5.8
Power-On Self Test
When the ATCA-F140 is booted, U-boot executes a series of Power-On Self test (POST)
routines. These routines check the functionality of different controllers and other on-board
resources. The result is stored in memory and has the following format.
Information about the POST status can also be obtained by reading the SYS FW
PROGRESS IPMI sensor. Depending on the POST status, the sensor holds the following
values.
Table 5-3
POST Result Format
Offset
Description
0x0
Magic word: 0xAA55FCE0
0x4
CRC32 checksum over the POST result string
0x8
POST result string. This is a zero-terminated string based on the following XML-
like syntax:[<T=tag>[<E>Error_description</E>]*</T>]*
tag
identifies the device that was tested. If no POST error was detected, then the
closing tag
</T>
follows immediately after the opening tag.
Error_Description
contains an error description of the corresponding <T>
tag. Note that the <T> tags can be nested, if for example several subtests are
performed in one device. See the following example.
<T=FPGA></T>
<T=DRAM><E>Address line</E></T>
<T=PCI><T=BIX></T><T=FIX2></T><T=FIX1></T></T>
<T=SPI><T=BEXT></T></T>
<T=I2C><T=CTRL1></T><T=CTRL2></T></T>
<T=MDIO><T=PHY0></T><T=PHY1></T><T=PHY2><
/T><T=PHY3></T></T>
Table 5-4
Post Results in SYS FW PROGRESS IPMI Sensor Reading Data
Value
Description
0x01
No memory detected
0x02
Memory error. The address and data line test failed.
0x0b
U-boot image CRC mismatch detected
0x0D
Wrong CPU speed
0xfd
SMART EC specific POST error code. For more information, see
PROGRESS IPMI Sensor - POST Error Event Codes on page 120
0x00
One of the remaining POST errors was detected
