112
ATCA-F140 Series Installation and Use (6806800M67S)
Functional Description
Functional Description
4.13
JTAG Support
The ATCA-F140 JTAG configuration consists of multiple JTAG chains controlled by a JTAG
multiplexer. This device has seven local JTAG slave ports. The ATCA-F140 has devices
which reside in the 3.3V management power and the 12V payload power domains. The
JTAG multiplexer, the power control CPLD and the H8S processor are powered from 3.3V
management power. The rest of the JTAG devices are powered from payload power.
When the Asset JTAG programming cable is installed on the header, the payload power
bypass enable signal is grounded, enabling the +12V payload power supply and each of
the on-board point of load supplies. This allows all of the JTAG devices to be accessed
regardless of the state of the power control CPLD.
4.14
Real Time Clock
An external 32.768kHz crystal sources the internal real time clock inside ICH10R with a
frequency tolerance of 20PPM. The RTC is fully DS1287, MC14618, PC87911 and Y2K
compliant and provides 256 bytes of backed up CMOS RAM (of which 14 bytes containing
the RTC time and date info and RTC configuration). During power-down, the RTC
consumes 0.9uA/hr. The optional power-down backup method uses a Super CAP with a 1
Farad capacity. This provides 300 hours of RTC/SRAM backup. The default battery is an
ex3V lithium battery with a capacity of 200mAh, which provides three years of
backup.
IPMC LPC
SERIRQ
To FPGA LPC
interface only
10
Persistent
Memory
FPGA
IRQ11_L
FPGA
Active
Low
LVTTL 3.3
11
Table 4-9
Interrupt Mapping (continued)
Interrupt Source
Port Signal
Source
Type
Voltage
P2020
IRQ
