Functional Description
ATCA-F140 Series Installation and Use (6806800M67S)
97
BCM84740 microcode flash programming - The same SPI controller in the FPGA
is used as with configuration flash programming, but now AUX_SS2 is driven
instead of CSO_B (which is deasserted), allowing SPI flash 4 to be programmed.
BCM8727 microcode loading - The SPI port from the BCM8727 is routed to
AUX_CS, CCLK, MOSI and DIN pins in the FPGA to allow the microcode to be
read from SPI flash 3.
BCM84740 microcode loading - The SPI port from the BCM84740 devices are
routed to AUX_CS, CCLK, MOSI and DIN pins in the FPGA to allow the microcode
to be read from SPI flash 4.
4.6
Boot and User Flashes
4.6.1
Boot Flash
On the ATCA-F140, two 256 Mbit NOR flash devices are used as boot devices for the
service processor. The flash devices used will be Micron PC28F256P33BF or equivalent
devices. The data bus width to the flash devices is 16 bit, supporting word accesses only.
4.6.2
Boot Bank Selection and Reprogramming
By default, the payload processor boots from Boot Flash device #1. An IPMI OEM
command can be used to send a message to the IPMC to change the boot device. The
IPMC provides an IPMI sensor to control the signal BOOT_BANK. If the BOOT_BANK
signal is set high, the payload processor will boot from Boot Flash device #2 after reset.
The boot device from which the service processor has booted (active bank) is write
protected, whereas the redundant boot device can be erased and reprogrammed. This is
to prevent inadvertent corruption of both boot banks during firmware updates.
For example, in order to update the firmware in both devices, the user could boot from flash
device #1 and update flash device #2. Then the user must switch the active boot bank and
boot from flash device #2, which would then enable writes to flash device #1. At this point,
the blade has successfully booted the updated firmware image in flash device #2, so it is
safe to allow the firmware update of flash device #1
