Saia-Burgess Controls AG
Manual I/O-modules for PCD1 │ PCD2 series │ Document 27-600 – Release ENG09 │ 2019-05-01
6-115
I/O modules PCD3
PCD3.H100
6
Block diagram
A
B
SC x1 x2
CCO
U+
Input
Interface
Output
Interface
Counter Flag
Counter enable
Counter Mode
up/down
Clock
Set CCO
PCD BUS
Input
filters
Inputs
Mode
Counter Status Flag
Counter
Set
Set CCO
Operating principle
This can be largely derived from the block diagram. It is only necessary to add
some explanation about the counter output circuit:
The output of the internal counter is identified as “Counter Flag”. The user has
no hardware access to it. This counter flag is set to “1” whenever the counter is
loaded or by means of a separate instruction.
The flag is set to “0”
in up-counting mode: when counter value 65,535 is
reached
in down-counting mode: when counter value 0 is reached
To reset a CCO hardware output which had previously been set high by the user
program, it is necessary to differentiate between two cases:
a) count range between 0…65,535 (normal case)
b) count range exceeding 65,535
Case a): Resetting the counter flag results in a simultaneous reset of the CCO
output.
Counter Flag
Reset Enable
CCO
0
50'000
The “Reset-Enable” should be activated
before
the counter reaches zero.