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USB2.0 DEVICE
S3C2416X RISC MICROPROCESSOR
16-16
8.9 EP0 STATUS REGISTER (EP0SR)
This register stores status information of the Endpoint 0. These status information are set automatically by the
core when corresponding conditions are met. After reading the bits, MCU should write 1 to clear them.
Register
Address
R/W
Description
Reset Value
EP0SR
0x4980_0024
R/W EP0 status register
0x0
EP0SR
Bit
R/W
Description
Initial State
[31:7]
−
Reserved
LWO
[6]
R
Last Word Odd
Low informs that the last word of a packet in FIFO has an
invalid upper byte.
This bit is cleared automatically after the MCU reads it from
the FIFO.
0
[5]
−
Reserved
SHT
[4]
R/C Stall Handshake Transmitted.
SHT informs that STALL handshake due to stall condition is
sent to Host.
This bit is an interrupt source. This bit is cleared when the
MCU writes 1.
0
[3:2]
−
Reserved
TST
[1]
R/C Tx successfully received.
TST is set by core after core sends TX data to Host and
receives ACK successfully. TST is one of the interrupt
sources.
0
RSR
[0]
R/C Rx successfully received.
RSR is set by core after core receives error free packet from
Host and sent ACK back to Host successfully.
RSR is one of the interrupt sources.
0
Summary of Contents for S3C2416
Page 122: ...BUS MATRIX EBI S3C2416X RISC MICROPROCESSOR 3 4 NOTES ...
Page 204: ...DMA CONTROLLER S3C2416X RISC MICROPROCESSOR 8 18 NOTES ...
Page 284: ...WATCHDOG TIMER S3C2416X RISC MICROPROCESSOR 11 6 NOTES ...
Page 320: ...REAL TIME CLOCK S3C2416X RISC MICROPROCESSOR 13 16 NOTES ...
Page 344: ...UART S3C2416X RISC MICROPROCESSOR 14 24 NOTES ...
Page 380: ...USB2 0 DEVICE S3C2416X RISC MICROPROCESSOR 16 34 NOTES ...
Page 432: ...2D S3C2416X RISC MICROPROCESSOR 18 38 NOTES ...
Page 446: ...HS_SPI CONTROLLER S3C2416X RISC MICROPROCESSOR 19 14 NOTES ...
Page 604: ...S3C2416X RISC MICROPROCESSOR S3C2416X RISC MICROPROCESSOR 23 22 NOTES ...
Page 638: ...PCM AUDIO INTERFACE S3C2416X RISC MICROPROCESSOR 25 18 NOTES ...
Page 670: ...ELECTRICAL DATA S3C2416X RISC MICROPROCESSOR 26 32 NOTES ...