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Samsung S3C2416, User Manual

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S3C2416X RISC MICROPROCESSOR

 

 

USB2.0 DEVICE 

 

16-13 

8.7  SYSTEM STATUS REGISTER (SSR) 

This register reports operational status of the USB 2.0 Function Core, especially about error status and power 

saving mode status. Except the line status, every status bits in the System Status Register could be an interrupt 

sources. When the register is read after an interrupt due to certain system status changes, MCU should write 

back 1 to the corresponding bits to clear it. 

Register 

Address 

R/W 

Description 

Reset Value

SSR 0x4980_001C 

R/C 

Test 

register 

0x0 

 

SSR 

Bit 

R/W 

Description 

Initial State

 [31:16] 

− 

Reserved  

BAERR 

[15] 

R/C  Byte Align Error 

If error interrupt enable bit of SCR register is set to 1, 

BAERR is set to 1 when byte alignment error is detected. 

0 

TMERR 

[14] 

R/C  Timeout Error  

If error interrupt enable bit of SCR register is set to 1, 

TMERR is set to 1 when timeout error is detected. 

0 

BSERR 

[13] 

R/C  Bit Stuff Error 

If error interrupt enable bit of SCR register is set to 1, 

BSERR is set to 1 when bit stuff error is detected. 

0 

TCERR 

[12] 

R/C  Token CRC Error 

If error interrupt enable bit of SCR register is set to 1, 

BSERR is set to 1 when CRC error in token packet is 

detected. 

0 

DCERR 

[11] 

R/C  Data CRC Error 

If error interrupt enable bit of SCR register is set to 1, 

DCERR is set to 1 when CRC error in data packet is 

detected. 

0 

EOERR 

[10] 

R/C  EB OVERRUN Error 

If error interrupt enable bit of SCR register is set to 1, 

EOERR is set to 1 when EB overrun error in transceiver is 

detected. 

0 

 [9:8] 

− 

Reserved  

TBM 

[7] 

R/C  Toggle Bit Mismatch. 

If error interrupt enable bit of SCR register is set to 1, TBM 

is set to 1 when Toggle mismatch is detected. 

0 

DP 

[6] 

R 

DP Data Line State  

DP informs the status of D+ Line 

0 

DM 

[5] 

R 

DM Data Line State  

DM informs the status of D- Line 

0 

HSP [4] 

R 

Host 

Speed 

0 = Full Speed 

1 = High Speed 

0 

Summary of Contents for S3C2416

Page 1: ...USER S MANUAL S3C2416 16 32 Bit RISC Microprocessor August 2008 REV 1 00 Confidential Proprietary of Samsung Electronics Co Ltd Copyright 2008 Samsung Electronics Inc All Rights Reserved ...

Page 2: ...r sustain life or for any other application in which the failure of the Samsung product could create a situation where personal injury or death may occur Should the Buyer purchase or use a Samsung product for any such unintended or unauthorized application the Buyer shall indemnify and hold Samsung and its officers employees subsidiaries affiliates and distributors harmless against all claims cost...

Page 3: ...PRODUCT NAME S3C2416 RISC Microprocessor DOCUMENT NAME S3C2416 User s Manual Revision 1 00 DOCUMENT NUMBER 21 10 S3 C2416 082008 EFFECTIVE DATE August 2008 DIRECTIONS Revision 1 00 REVISION HISTORY Revision No Description of Change Refer to Author s Date 1 00 Initial release AP app part August 27 2008 ...

Page 4: ...REVISION DESCRIPTIONS FOR REVISION 1 00 Chapter Chapter Name Page Subjects Major changes comparing with last version ...

Page 5: ...og Reset 2 4 4 4 Software Reset 2 5 4 5 Wakeup Reset 2 5 5 Clock Management 2 6 5 1 Clock Generation Overview 2 6 5 2 Clock Source Selection 2 6 5 3 PLL Phase Locked Loop 2 8 5 4 Change PLL Settings In Normal Operation 2 8 5 5 System Clock Control 2 9 5 6 ARM BUS Clock Divide Ratio 2 10 5 7 Examples for configuring clock regiter to produce specific frequency of AMBA clocks 2 11 5 8 ESYSCLK Control...

Page 6: ...nd wake up from sleep mode 2 34 8 6 System Controller Status Registers WKUPSTAT and RSTSTAT 2 35 8 7 Bus Configuration Register BUSPRI0 BUSPRI1 and BUSMISC 2 36 8 8 Information Register 0 1 2 3 2 37 8 9 USB PHY Control register PHYCTRL 2 38 8 10 USB PHY Power Control Register PHYPWR 2 39 8 11 USB Reset Control Register URSTCON 2 39 8 12 USB Clock Control Register UCLKCON 2 40 Chapter 3 Bus Matrix ...

Page 7: ... Enable Assertion Delay Control Registers 0 5 5 15 4 5 Bank Write Enable Assertion Delay Control Registers 0 5 5 16 4 6 Bank Control Registers 0 5 5 17 4 7 Bank Onenand Type Selection Register 5 19 4 8 SMC Status Register 5 19 4 9 SMC Control Register 5 20 Chapter 6 Mobile DRAM Controller 1 Overview 6 1 2 Block Diagram 6 2 3 Mobile DRAM Initialization Sequence 6 3 3 1 Mobile DRAM SDRAM or mobile D...

Page 8: ...C Programming Guide DECODING 7 9 11 Memory Mapping NAND boot and Other boot 7 10 12 NAND Flash Memory Configuration 7 11 13 NAND Flash Controller Special Registers 7 12 13 1 NAND Flash Controller Register Map 7 12 13 2 Nand Flash Configuration Register 7 13 13 3 Control Register 7 15 13 4 Command Register 7 17 13 5 Address Register 7 17 13 6 Data Register 7 17 13 7 Main Data area ECC Register 7 18...

Page 9: ... 8 Current Destination Register DCDST 8 15 4 9 DMA Mask Trigger Register DMASKTRIG 8 16 4 10 DMA Requeset Selection Register DMAREQSEL 8 17 Chapter 9 Interrupt Controller 1 Overview 9 1 1 1 Interrupt Controller Operation 9 3 1 2 Interrupt Sources 9 4 1 3 Interrupt Priority Generating Block 9 6 1 4 Interrupt Priority 9 7 2 Interrupt Controller Special Registers 9 8 2 1 Source Pending SRCPND Registe...

Page 10: ...GPFCON GPFDAT GPFUDP 10 20 3 7 PORT G Control Registers GPGCON GPGDAT GPGUDP 10 21 3 8 PORT H Control Registers GPHCON GPHDAT GPHUDP 10 23 3 9 PORT J Control Registers GPJCON GPJDAT GPJUDP GPJSEL 10 25 3 10 PORT K Control Registers GPKCON GPKDAT GPKUDP 10 27 3 11 PORT L Control Registers GPLCON GPLDAT GPLUDP GPLSEL 10 29 3 12 PORT M Control Registers GPMCON GPMDAT GPMUDP 10 31 3 13 Miscellaneous C...

Page 11: ...e Width Modulation PWM 12 8 2 7 Output Level Control 12 9 2 8 DEAD Zone Generator 12 10 2 9 DMA Request Mode 12 11 3 PWM Timer Control Registers 12 12 3 1 Timer Configuration Register0 TCFG0 12 12 3 2 Timer Configuration Register1 TCFG1 12 13 3 3 Timer Control TCON Register 12 14 3 4 Timer 0 Count Buffer Register Compare Buffer Register TCNTB0 TCMPB0 12 16 3 5 Timer 0 Count Observation Register TC...

Page 12: ...ART Line Control Register 14 12 3 2 UART Control Register 14 13 3 3 UART FIFO Control Register 14 15 3 4 UART Modem Control Register 14 16 3 5 UART Tx Rx Status Register 14 17 3 6 UART Error Status Register 14 18 3 7 UART FIFO Status Register 14 19 3 8 UART Modem Status Register 14 20 3 9 UART Transmit BUffer register Holding Register FIFO Register 14 21 3 10 UART Receive BUffer Register Holding R...

Page 13: ... Register SSR 16 13 8 8 System Control Register SCR 16 15 8 9 EP0 Status Register EP0SR 16 16 8 10 EP0 Control Register EP0CR 16 17 8 11 Endpoint Buffer Register EP BR 16 18 8 12 Endpoint Status Register ESR 16 19 8 13 Endpoint Control Register ECR 16 21 8 14 Byte read Count Register BRCR 16 22 8 15 Byte Write Count Register BWCR 16 23 8 16 MAX Packet Register MPR 16 24 8 17 DMA Control Register D...

Page 14: ...ontrol IICCON Register 17 11 2 2 Multi Master IIC Bus Control Status IICSTAT Register 17 12 2 3 Multi Master IIC Bus Address IICADD Register 17 13 2 4 Multi Master IIC Bus Transmit Receive Data Shift IICDS Register 17 13 2 5 Multi Master IIC Bus Line Control IICLC Register 17 14 Chapter 18 2D 1 Introduction 18 1 1 1 Features 18 1 2 Color Format Conversion 18 2 3 Command FIFO 18 3 4 Rendering Pipel...

Page 15: ...ply Sequence 20 4 4 3 SD Clock Stop Sequence 20 5 4 4 SD Clock Frequency Change Sequence 20 5 4 5 SD Bus Power Control Sequence 20 6 4 6 Change Bus Width Sequence 20 7 4 7 Timeout Setting for DAT Line 20 8 4 8 SD Transaction Generation 20 8 4 9 SD Command Issue Sequence 20 9 4 10 Command Complete Sequence 20 10 4 11 Transaction Control with Data Transfer Using DAT Line 20 12 4 12 Abort Transaction...

Page 16: ...rol Register 2 20 64 5 28 Control Register 3 20 67 5 29 Debug Register 20 68 5 30 Control Register 4 20 68 5 31 Force Event Register for Auto CMD12 Error Status 20 69 5 32 Force Event Register for Error Interrupt Status 20 70 5 33 ADMA Error Status Register 20 71 5 34 ADMA System Address Register 20 73 5 35 HOST Controller Version Register 20 74 Chapter 21 LCD Controller 1 Overview 21 1 1 1 Featur...

Page 17: ...0 Chapter 23 IIS Multi Audio Interface 1 Overview 23 1 2 Feature 23 1 3 Signals 23 1 4 Block Diagram 23 2 5 Functional Descriptions 23 2 5 1 Master Slave Mode 23 3 5 2 DMA Transfer 23 4 6 Audio Serial Data Format 23 5 6 1 IIS Bus Format 23 5 6 2 MSB Left Justified 23 5 6 3 LSB Right Justified 23 5 6 4 Sampling Frequency and Master Clock 23 7 6 5 IIS Clock Mapping Table 23 7 7 Programming Guide 23 ...

Page 18: ...dec Reset 24 10 7 AC97 Controller State Diagram 24 11 8 AC97 Controller Special Registers 24 12 8 1 AC97 Special Funcion Register Summary 24 12 8 2 AC97 Global Control Register AC_GLBCTRL 24 13 8 3 AC97 Global Status Register AC_GLBSTAT 24 14 8 4 AC97 Codec Command Register AC_CODEC_CMD 24 14 8 5 AC97 Codec Status Register AC_CODEC_STAT 24 15 8 6 AC97 PCM Out In Channel Fifo Address Register AC_PC...

Page 19: ...ister 25 6 3 5 PCM CLK Control Register 25 8 3 6 The PCM Tx FIFO Register 25 9 3 7 PCM Rx FIFO Register 25 10 3 8 PCM Interrupt Control Register 25 11 3 9 PCM Interrupt Status Register 25 14 3 10 PCM FIFO Status Register 25 16 3 11 PCM Interrupt Clear Register 25 17 Chapter 26 Electrical Data 1 Absolute Maximum Ratings 26 1 2 Recommended Operating Conditions 26 2 3 D C Electrical Characteristics 2...

Page 20: ...ck Diagram 5 3 5 2 SMC Core Block Diagram 5 3 5 3 External Memory Two Output Enable Delay State Read 5 4 5 4 Read Timing Diagram DRnCS 1 DRnOWE 0 5 4 5 5 Read Timing Diagram DRnCS 1 DRnOWE 1 5 5 5 6 External Burst ROM with WSTRD 2 and WSTBRD 1 Fixed Length Burst Read 5 6 5 7 External Synchronous Fixed Length Four Transfer Burst Read 5 7 5 8 External Memory Two Write Enable Delay State Write 5 8 5 ...

Page 21: ...andshake Mode Comparison 8 5 8 3 Burst 4 Transfer size 8 6 8 4 Single service Demand Mode Single Transfer Size 8 7 8 5 Single service Handshake Mode Single Transfer Size 8 7 8 6 Whole service Handshake Mode Single Transfer Size 8 7 9 1 Interrupt Process Diagram 9 1 9 2 Interrupt Group Multiplexing Diagram 9 2 9 3 Priority Generating Block 9 6 11 1 Watchdog Timer Block Diagram 11 2 12 1 16 bit PWM ...

Page 22: ...USB Host Controller Block Diagram 15 1 16 1 USB2 0 Block Diagram 16 2 16 2 USB2 0 Function Block Diagram 16 3 16 3 OUT Transfer Operation Flow 16 32 16 4 IN Transfer Operation Flow 16 33 17 1 IIC Bus Block Diagram 17 2 17 2 Start and Stop Condition 17 3 17 3 IIC Bus Interface Data Format 17 4 17 4 Data Transfer on the IIC Bus 17 5 17 5 Acknowledge on the IIC Bus 17 5 17 6 Operations for Master Tra...

Page 23: ...trol with Data Transfer Using DAT Line Sequence Using DMA 20 15 20 13 Card Detect State 20 34 20 14 Timing of Command Inhibit DAT and Command Inhibit CMD with data transfer 20 35 20 15 Timing of Command Inhibit DAT for the case of response with busy 20 35 20 16 Timing of Command Inhibit CMD for the case of no response command 20 35 21 1 LCD Controller Block diagram 21 1 21 2 Block diagram of the D...

Page 24: ... 10 23 5 TX FIF0 Structure for BLC 10 24 bits channel 23 11 23 6 RX FIFO Structure for BLC 00 or BLC 01 23 13 23 7 RX FIF0 Structure for BLC 10 24 bits channel 23 14 24 1 AC97 Block Diagram 24 2 24 2 Internal Data Path 24 3 24 3 AC97 Operation Flow Chart 24 4 24 4 Bi directional AC link Frame with Slot Assignments 24 5 24 5 AC link Output Frame 24 6 24 6 AC link Input Frame 24 8 24 7 AC97 Power do...

Page 25: ... 26 12 26 12 SMC Wait Timing 26 13 26 13 Nand Flash Timing 26 14 26 14 SDRAM READ WRITE Timing Trp 2 Trcd 2 Tcl 2 DW 16 bit 26 15 26 15 DDR2 Timing 26 16 26 16 SDRAM MRS Timing 26 17 26 17 SDRAM Auto Refresh Timing Trp 2 Trc 4 26 18 26 18 External DMA Timing Handshake Single transfer 26 19 26 19 TFT LCD Controller Timing 26 19 26 20 IIS Interface Timing I2S Master Mode Only 26 20 26 21 IIS Interfa...

Page 26: ... S sustain previous value 2 5 2 2 Clock source selection for the main PLL and clock generation logic 2 6 2 3 Clock Source Selection for the EPLL 2 7 2 4 PLL Clock Generator Condition 2 7 2 5 Clock Division Ratio of MPLL Region 2 10 2 6 ESYSCLK Control 2 12 2 7 The Status of PLL and ARMCLK After Wake up 2 19 2 8 Power Saving Mode Entering Exiting Condition 2 20 2 9 System Controller Address Map 2 2...

Page 27: ...and Command Timeout Error 20 52 20 5 The Relation Between Command CRC Error and Command Timeout Error 20 60 20 6 Maximum Current Value Definition 20 63 21 1 25BPP A 8 8 8 Palette Data Format 21 20 21 2 19BPP A 6 6 6 Palette Data Format 21 21 21 3 16BPP A 5 5 5 Palette Data Format 21 21 21 4 Alpha Value Selection Table for Blending 21 23 21 5 Relation between VCLK and CLKVAL Freq of Video Clock Sou...

Page 28: ...26 11 Memory Interface Timing Constants SDRAM 26 25 26 12 DMA Controller Module Signal Timing Constants 26 26 26 13 TFT LCD Controller Module Signal Timing Constants 26 26 26 14 IIS Controller Module Signal Timing Constants I2S Master Mode Only 26 26 26 15 IIS Controller Module Signal Timing Constants I2S Slave Mode Only 26 27 26 16 IIC BUS Controller Module Signal Timing 26 27 26 17 High Speed SP...

Page 29: ...e set of common system peripherals the S3C2416X minimizes overall system costs and eliminates the need to configure additional components The integrated on chip functions that are described in this document include Around 400MHz 1 3V 266MHz TBDV Core 1 8V 2 5V 3 0V 3 3V ROM SRAM 1 8V 2 5V mSDR mDDR DDR2 SDRAM 1 8V 2 5V 3 3V external I O microprocessor with 16KB I D Cache MMU External memory contro...

Page 30: ... signals to expand the bus cycle Supports self refresh mode in SDRAM for power down Supports various types of ROM for booting NOR Flash EEPROM OneNAND IROM and others 2 1 3 NAND Flash Supports booting from NAND flash memory by selecting OM as IROM boot mode Only 8bit Nand and 8ECC is supported when it boots 64KB for internal SRAM Buffer 8KB internal buffer for booting Supports storage memory for N...

Page 31: ...9 General Purpose Input Output Ports 16 external interrupt ports 138 Multiplexed input output ports 2 1 10 DMA Controller 6 ch DMA controller Supports memory to memory IO to memory memory to IO and IO to IO transfers Burst transfer mode to enhance the transfer rate 2 1 11 LCD Controller Supports 1 2 4 or 8 bpp bit per pixel palette color displays for color Supports 16 24 bpp non palette true color...

Page 32: ...t AC97 for audio interface with DMA based operation 16 bit Stereo Audio 2 1 19 PCM Audio Interface Mono 16bit PCM 1 ports audio interface Master mode only this block always sources the main shift clock Input 16bit 32depth and output 16bit 32depth FIFOs to buffer data 2 1 20 USB Host 2 port USB Host Complies with OHCI Rev 1 0 Compatible with USB Specification version 1 1 2 1 21 USB Device 1 port US...

Page 33: ...S3C2416X RISC MICROPROCESSOR PRODUCT OVERVIEW 1 5 3 BLOCK DIAGRAM Figure 1 1 S3C2416X Block Diagram ...

Page 34: ...PRODUCT OVERVIEW S3C2416X RISC MICROPROCESSOR 1 6 4 PIN ASSIGNMENTS Figure 1 2 S3C2416X Pin Assignments 330 FBGA 0 65mm pitch Top view ...

Page 35: ... 89 VSSiarm U7 16 VDD_SRAM C5 53 RGB_VD 3 GPC11 N8 90 nXDREQ I2SSDO_2 GPB1 0 U5 17 VSS_SRAM E2 54 RGB_VD 4 GPC12 M1 91 UARTCLK GPH12 Y4 18 RDATA 15 H7 55 RGB_VD 5 GPC13 N6 92 nCTS 0 GPH8 R7 19 RDATA 14 E1 56 RGB_VD 6 GPC14 N1 93 nRTS 0 GPH9 W5 20 RDATA 13 J4 57 RGB_VD 7 GPC15 P6 94 TXD 0 GPH0 P8 21 RDATA 12 F2 58 RGB_VD 8 GPD0 N2 95 RXD 0 GPH1 V6 22 RDATA 11 J6 59 RGB_VD 9 GPD1 P7 96 nCTS 1 GPH10 ...

Page 36: ...PRODUCT OVERVIEW S3C2416X RISC MICROPROCESSOR 1 8 37 VSSi H11 74 VDD_LCD U1 111 I2SSCLK GPE1 AC_SYNC PCM_SCLK Y9 ...

Page 37: ... 0 GPL0 V12 171 EINT 1 GPF1 T18 213 VSS33T J17 130 SD1_DAT 1 GPL1 W13 172 EINT 2 GPF2 P17 214 VDD33 G18 131 SD1_DAT 2 GPL2 U12 173 EINT 3 GPF3 R18 215 VDD33 G19 132 SD1_DAT 3 GPL3 Y14 174 EINT 4 GPF4 N17 216 SDATA 31 GPK15 J18 133 SD0_CLK GPE5 V13 175 EINT 5 GPF5 U19 217 SDATA 30 GPK14 G20 134 SD0_CMD GPE6 W14 176 EINT 6 GPF6 M17 218 SDATA 29 GPK13 J15 135 SD0_DAT 0 GPE7 U13 177 EINT 7 GPF7 U20 21...

Page 38: ...PRODUCT OVERVIEW S3C2416X RISC MICROPROCESSOR 1 10 153 AIN 1 U14 195 EINT 10 GPG2 K15 237 SDATA 14 C18 ...

Page 39: ...ATA 0 A17 294 RADDR 23 GPA8 G10 252 VDD_SDRAM D19 295 RADDR 22 GPA7 A7 253 VSS_SDRAM D18 296 RADDR 21 GPA6 H10 254 DQS 1 F14 297 RADDR 20 GPA5 B7 255 DQS 0 C14 298 RADDR 19 GPA4 C9 256 DQM 3 GPA26 D14 299 RADDR 18 GPA3 C7 257 DQM 2 GPA25 B16 300 RADDR 17 GPA2 D9 258 DQM 1 C13 301 RADDR 16 GPA1 A6 259 DQM 0 A16 302 RADDR 15 F9 260 nSCS 0 F13 303 RADDR 14 B6 261 nSCS 1 B15 304 RADDR 13 G9 262 nSWE D...

Page 40: ...O H pvhbsudtbrt 11 nFRE GPA20 nFRE O H pvhbsudtbrt 12 nFCE GPA22 nFCE O H pvhbsudtbrt 13 FRnB GPM1 FRnB I pvhbsudtbrt 14 VDDi VDDi P vddivh_alv 15 VSSi VSSi P vssipvh_alv 16 VDD_SRAM VDD_SRAM P vddtvh_alv 17 VSS_SRAM VSS_SRAM P vsstvh_alv 18 RDATA15 RDATA15 Hi z pvhbsudtbrt 19 RDATA14 RDATA14 Hi z pvhbsudtbrt 20 RDATA13 RDATA13 Hi z pvhbsudtbrt 21 RDATA12 RDATA12 Hi z pvhbsudtbrt 22 RDATA11 RDATA1...

Page 41: ...I pvhbsudtart 47 GPC5 GPC5 I pvhbsudtart 48 GPC6 GPC6 I pvhbsudtart 49 GPC7 GPC7 I pvhbsudtart 50 RGB_VD0 GPC8 GPC8 I pvhbsudtart 51 RGB_VD1 GPC9 GPC9 I pvhbsudtart 52 RGB_VD2 GPC10 GPC10 I pvhbsudtart 53 RGB_VD3 GPC11 GPC11 I pvhbsudtart 54 RGB_VD4 GPC12 GPC12 I pvhbsudtart 55 RGB_VD5 GPC13 GPC13 I pvhbsudtart 56 RGB_VD6 GPC14 GPC14 I pvhbsudtart 57 RGB_VD7 GPC15 GPC15 I pvhbsudtart 58 RGB_VD8 GP...

Page 42: ...hbsudtart 82 TOUT2 GPB2 GPB2 I pvhbsudtart 83 TOUT3 GPB3 GPB3 I pvhbsudtart 84 TCLK GPB4 GPB4 I pvhbsudtart 85 nXBACK GPB5 GPB5 I pvhbsudtart 86 nXBREQ GPB6 RTCK RTCK I pvhbsudtart 87 nXDACK GPB9 I2SSDO_1 GPB9 I pvhbsudtart 88 89 VSSiarm VSSiarm P vssicvlh_alv 90 nXDREQ GPB10 I2SSDO_2 GPB10 I pvhbsudtart 91 EXTUARTCLK GPH12 GPH12 I pvhbsudtart 92 nCTS0 GPH8 GPH8 I pvhbsudtart 93 nRTS0 GPH9 GPH9 I ...

Page 43: ...E11 GPE11 I pvhbsudtart 116 SPIMOSI GPE12 GPE12 I pvhbsudtart 117 SPICLK GPE13 GPE13 I pvhbsudtart 118 TXD2 GPH4 GPH4 I pvhbsudtart 119 RXD2 GPH5 GPH5 I pvhbsudtart 120 TXD3 GPH6 nRTS2 GPH6 I pvhbsudtart 121 RXD3 GPH7 nCTS2 GPH7 I pvhbsudtart 122 SS GPL13 GPL13 I pvhbsudtart 123 SD1_CLK GPL9 GPL9 I pvhbsudtart 124 SD1_CMD GPL8 GPL8 I pvhbsudtart 125 VDD_SD VDD_SD P vddtvh_alv 126 VSS_SD VSS_SD P v...

Page 44: ...4 AI pvhbr 151 AIN3 AIN3 AI pvhbr 152 AIN2 AIN2 AI pvhbr 153 AIN1 AIN1 AI pvhbr 154 AIN0 AIN0 AI pvhbr 155 Vref Vref AI pvhbr 156 VDDA_ADC VDDA_ADC P vddtvh_alv 157 VDD_RTC VDD_RTC P vddrtcvh_alv 158 Xtirtc Xtirtc AI pvhsosca 159 Xtortc Xtortc AO pvhsosca 160 OM 4 OM 4 I pvhbsudtart_alv 161 OM 3 OM 3 I pvhbsudtart_alv 162 OM 2 OM 2 I pvhbsudtart_alv 163 OM 1 OM 1 I pvhbsudtart_alv 164 OM 0 OM 0 I ...

Page 45: ...DI I pvhbsudtart 188 TCK TCK I pvhbsudtart 189 nTRST nTRST I pvhbsudtart 190 DP DP AI usb6002x1_t 191 DN DN AI usb6002x1_t 192 nRSTOUT nRSTOUT O H O L pvhbsudtart 193 EINT8 GPG0 GPG0 I pvhbsudtart_alv 194 EINT9 GPG1 GPG1 I pvhbsudtart_alv 195 EINT10 GPG2 GPG2 I pvhbsudtart_alv 196 EINT11 GPG3 GPG3 I pvhbsudtart_alv 197 VDD_OP3 VDD_OP3 P vddtvh_alv 198 VSS_OP3 VSS_OP3 P vsstvh_alv 199 EINT12 GPG4 G...

Page 46: ...SDATA25 Hi z pvmbsudtbrt 225 SDATA24 GPK8 SDATA24 Hi z pvmbsudtbrt 226 SDATA23 GPK7 SDATA23 Hi z pvmbsudtbrt 227 SDATA22 GPK6 SDATA22 Hi z pvmbsudtbrt 228 SDATA21 GPK5 SDATA21 Hi z pvmbsudtbrt 229 SDATA20 GPK4 SDATA20 Hi z pvmbsudtbrt 230 SDATA19 GPK3 SDATA19 Hi z pvmbsudtbrt 231 SDATA18 GPK2 SDATA18 Hi z pvmbsudtbrt 232 SDATA17 GPK1 SDATA17 Hi z pvmbsudtbrt 233 SDATA16 GPK0 SDATA16 Hi z pvmbsudtb...

Page 47: ...tbrt 259 DQM0 DQM0 O H O L pvmbsudtbrt 260 nSCS 0 nSCS 0 O H O H pvmbsudtbrt 261 nSCS 1 nSCS 1 O H O H pvmbsudtbrt 262 nSWE nSWE O H O H pvmbsudtbrt 263 SCLK SCLK O L O SCLK pvmbsudtbrt 264 VDDi VDDi P vddivh_alv 265 VSSi VSSi P vssipvh_alv 266 nSCLK nSCLK O H O nSCLK pvmbsudtbrt 267 SCKE SCKE O L O L pvmbsudtbrt 268 nSRAS nSRAS O H O H pvmbsudtbrt 269 nSCAS nSCAS O H O H pvmbsudtbrt 270 SADDR0 SA...

Page 48: ...95 RADDR22 GPA7 RADDR22 O L pvhbsudtbrt 296 RADDR21 GPA6 RADDR21 O L pvhbsudtbrt 297 RADDR20 GPA5 RADDR20 O L pvhbsudtbrt 298 RADDR19 GPA4 RADDR19 O L pvhbsudtbrt 299 RADDR18 GPA3 RADDR18 O L pvhbsudtbrt 300 RADDR17 GPA2 RADDR17 O L pvhbsudtbrt 301 RADDR16 GPA1 RADDR16 O L pvhbsudtbrt 302 RADDR15 RADDR15 O L pvhbsudtbrt 303 RADDR14 RADDR14 O L pvhbsudtbrt 304 RADDR13 RADDR13 O L pvhbsudtbrt 305 RA...

Page 49: ...RCS2 GPA13 nRCS2 O H pvhbsudtbrt 327 VDD_SDRAM VDD_SDRAM P Vddtvm_alv 328 VDD_SDRAM VDD_SDRAM P Vddtvm_alv 329 VDD_SDRAM VDD_SDRAM P vddtvm_alv 330 VDD_SRAM VDD_SRAM P vddtvh_alv NOTES 1 The BUS REQ shows the pin state at the external bus which is used by the other bus master 2 mark indicates the unchanged pin state at Bus Request mode 3 Hi z or Pre means Hi z or early state and it is determined b...

Page 50: ... Schmit Y Y Y 3 3 6 6 9 9 13 2mA pvhckdsrt I 1 8 2 5 3 3V Schmit N N pvhsosca OSC 1 8 2 5 3 3V Schmit N N X1 2 5 3 3 X2 1 8 pvhsoscbrt OSC 1 8 2 5 3 3V schmit Y N N X1 X2 X3 X4 Pvhtbr Bi 1 8 2 5 3 3V analog pvhtbr00_efuse Bi 1 8 2 5 3 3V analog pvmbsudtbrt Bi 1 8 2 5V schmit Y Y Y 4 9 9 8 14 8 19 7mA usb6002x1_t Bi 1 8 2 5 3 3V vddicvlh_alv PWR 1 3V vddivh_alv PWR 1 3V vddivh_usb_alv PWR 1 2V vddr...

Page 51: ...e held to L level for at least 4 OSCin after the processor power has been stabilized nRSTOUT O For external device reset control nRSTOUT nRESET nWDTRST SW_RESET SW_RESET nRSTCON of GPIO MISCCR PWREN O core power on off control signal nBATT_FLT I Probe for battery state Does not wake up at Sleep mode in case of low battery state If it isn t used it has to be High 3 3V OM 4 0 I OM 4 0 set operating ...

Page 52: ... mask DQS 1 0 O mDDR DDR2 Data Strobe SCLK O SDRAM clock nSCLK O mDDR DDR2 Conversion clock SCKE O SDRAM clock enable NAND Flash FCLE O Command latch enable FALE O Address latch enable nFCE O Nand flash chip enable nFRE O Nand flash read enable nFWE O Nand flash write enable FRnB I Nand flash ready busy SMC OneNAND RSMCLK I O SMC Clock RSMVAD O SMC Address Valid RSMBWAIT O SMC Burst Wait LCD Contr...

Page 53: ...clear to send input signal ch 0 1 nRTS 2 0 O UART request to send output signal ch 0 1 EXTUARTCLK I External clock input for UART TSADC AIN 9 0 AI ADC input 9 0 If do not use ADC function AIN 9 and AIN 7 pins are tied to VDDA_ADC Others are tied to GND When touch screen device is used A 6 A 7 A 8 and A 9 are used as YM YP XM and XP respectively Vref AI ADC reference voltage IIC Bus IICSDA IO IIC b...

Page 54: ...Crystal output XI_UDEV OSC Crystal input SPI SPIMISO IO SPIMISO is the master data input line when SPI is configured as a master When SPI is configured as a slave these pins reverse its role SPIMOSI IO SPIMOSI is the master data output line when SPI is configured as a master When SPI is configured as a slave these pins reverse its role SPICLK IO SPI clock nSS I SPI chip select only for slave mode ...

Page 55: ...iarm P S3C2416X core logic VDD for ARM core VDDi P S3C2416X core logic VDD for Internal block VDDA_MPLL P S3C2416X MPLL analog and digital VDD VDDA_EPLL P S3C2416X EPLL analog and digital VDD VDD_SDRAM P S3C2416X SDRAM I O Power 1 8V 2 5V VDD_SRAM P S3C2416X ROM SRAM I O Power VDD_OP1 P S3C2416X System I O Power 1 1 8 3 3V VDD_OP2 P S3C2416X System I O Power 2 1 8 3 3V VDD_OP3 P S3C2416X System I ...

Page 56: ... G S3C2416X ADC VSS VDD_USBOSC P USB 2 0 Oscillator Power 1 8 3 3V VDDI_UDEV P USB 2 0 PHY Power 1 2V VSSI_UDEV G USB 2 0 PHY Ground VDDA33C VDDA33T1 P USB 2 0 PHY Power 3 3V VSSA33C VSSA33T2 G USB 2 0 PHY Ground NOTE I O Input Output AI AO Analog I O ST Schmitt trigger P Power G Ground ...

Page 57: ...Operation Mode 0 X TAL 0 1 0 0 1 iROM EXTCLK iROM 0 Reserved Reserved 0 1 JTAG JTAG 0 X TAL 0 1 1 OneNAND Muxed 16 bit EXTCLK OneNAND Muxed 0 X TAL 0 1 8 bit EXTCLK 0 X TAL 1 0 1 1 1 OneNAND ROM ROM OneNAND Demuxed 16 bit EXTCLK ROM OneNAND Demuxed OM 0 selects the clock source of MPLL EPLL You can select different EPLL clock source with that of MPLL by software setting refer to SYSCON ...

Page 58: ...M nRCS5 SROM nRCS4 SROM nRCS3 SROM nRCS2 SROM nRCS1 SROM nRCS0 Using OneNAND for boot ROM SRAM 8KB SDRAM nSCS1 SDRAM nSCS0 SROM nRCS5 SROM nRCS4 ROM nRCS3 SROM nRCS2 SROM nRCS1 Internal iROM Using iROM for boot ROM MPORT1 MPORT0 0x1800_0000 0x0000_0000 0x0800_0000 0x1000_0000 0x2000_0000 0x2800_0000 0x3000_0000 0x3800_0000 0x40000_0000 SRAM 64KB Figure 1 3 Memory Map ...

Page 59: ... Reserved 0x5900_0000 Reserved 0x4B00_0700 Reserved 0x5800_0000 TSADC 0x4B00_0600 Reserved 0x5700_0000 RTC 0x4B00_0500 DMA5 0x5600_0000 IO Port 0x4B00_0400 DMA4 0x5500_0100 Reserved 0x4B00_0300 DMA3 0x5500_0000 IIS0 0x4B00_0200 DMA2 0x5400_0100 Reserved 0x4B00_0100 DMA1 0x5400_0000 IIC0 0x4B00_0000 DMA0 0x5300_0000 WDT 0x4AC0_0000 HS MMC0 0x5200_0000 HS SPI0 0x4A80_0000 HS MMC1 0x5100_0000 PWM 0x4...

Page 60: ...0080 0x0000000F W R W Bank4 idle cycle control register SMBIDCYR5 0x4F0000A0 0x0000000F W R W Bank5 idle cycle control register SMBWSTRDR0 0x4F000004 0x0000001 W R W Bank0 read wait state control register SMBWSTRDR1 0x4F000024 0x0000001F W R W Bank1 read wait state control register SMBWSTRDR2 0x4F000044 0x0000001F W R W Bank2 read wait state control register SMBWSTRDR3 0x4F000064 0x0000001F W R W ...

Page 61: ...2 0x4F000054 0x00303010 W R W Bank2 control register SMBCR3 0x4F000074 0x00303000 W R W Bank3 control register SMBCR4 0x4F000094 0x00303010 W R W Bank4 control register SMBCR5 0x4F0000B4 0x00303010 W R W Bank5 control register SMBSR0 0x4F000018 0x00000000 W R W Bank0 status register SMBSR1 0x4F000038 0x00000000 W R W Bank1 status register SMBSR2 0x4F000058 0x00000000 W R W Bank2 status register SM...

Page 62: ... control 2 INTMSK2 0X4A000048 0xFFFFFFFF W R W Interrupt mask control 2 INTPND2 0X4A000050 0x00000000 W R W Interrupt request status 2 INTOFFSET2 0X4A000054 0x00000000 W R Interrupt request source offset 2 PRIORITY_MODE2 0X4A000070 0x00000000 W R W Priority mode register 2 PRIORITY_UPDATE2 0X4A000074 0x0000007F W R W Priority update register 2 USB Host Controller HcRevision 0x49000000 W R W Contro...

Page 63: ...00104 R W DMA 1 initial source control DIDST1 0x4B000108 R W DMA 1 initial destination DIDSTC1 0x4B00010C R W DMA 1 initial destination control DCON1 0x4B000110 R W DMA 1 control DSTAT1 0x4B000114 R DMA 1 count DCSRC1 0x4B000118 R DMA 1 current source DCDST1 0x4B00011C R DMA 1 current destination DMASKTRIG1 0x4B000120 R W DMA 1 mask trigger DMAREQSEL1 0x4B000124 R W DMA1 Request Selection Register...

Page 64: ...SKTRIG4 0x4B000420 R W DMA 4 mask trigger DMAREQSEL4 0x4B000424 R W DMA4 Request Selection Register DISRC5 0x4B000500 W R W DMA 5 initial source DISRCC5 0x4B000504 R W DMA 5 initial source control DIDST5 0x4B000508 R W DMA 5 initial destination DIDSTC5 0x4B00050C R W DMA 5 initial destination control DCON5 0x4B000510 R W DMA 5 control DSTAT5 0x4B000514 R DMA 5 count DCSRC5 0x4B000518 R DMA 5 curre...

Page 65: ...formation register 2 INFORM3 0x4C00_007C 0x0000_0000 SLEEP mode information register 3 PHYCTRL 0x4C00_0080 0x0000_0000 USB PHY control register PHYPWR 0x4C00_0084 0x0000_0000 USB PHY power control register URSTCON 0x4C00_0088 0x0000_0000 USB PHY Reset control register UCLKCON 0x4C00_008C 0x0000_0000 USB PHY clock control register LCD Controller VIDCON0 0x4C80_0000 0x0000_0000 W R W Video control 0...

Page 66: ...value register W3KEYCON0 0x4C80_00C0 0x0000_0000 W R W Color key control register W3KEYCON1 0x4C80_00C4 0x0000_0000 W R W Color key value transparent value register W4KEYCON0 0x4C80_00C8 0x0000_0000 W R W Color key control register W4KEYCON1 0x4C80_00CC 0x0000_0000 W R W Color key value transparent value register WIN0MAP 0x4C80_00D0 0x0000_0000 W R W Window color control WIN1MAP 0x4C80_00D4 0x0000...

Page 67: ...ror bit pattern register NF8ECCERR0 0x4E000044 0x40000000 W R 8bit ECC error status0 register NF8ECCERR1 0x4E000048 0x00000000 W R 8bit ECC error status1 register NF8ECCERR2 0x4E00004C 0x00000000 W R 8bit ECC error status2 register NFM8ECC0 0x4E000050 W R Generated 8 bit ECC status0 register NFM8ECC1 0x4E000054 W R Generated 8 bit ECC status1 register NFM8ECC2 0x4E000058 W R Generated 8 bit ECC st...

Page 68: ...FCON2 0x50008008 UART 2 FIFO control UTRSTAT2 0x50008010 R UART 2 Tx Rx status UERSTAT2 0x50008014 UART 2 Rx error status UFSTAT2 0x50008018 UART 2 FIFO status UTXH2 0x50008020 B W UART 2 transmission hold URXH2 0x50008024 R UART 2 receive buffer UBRDIV2 0x50008028 W R W UART 2 baud rate divisor UDIVSLOT2 0x500802C Baud rate divisior decimal place register 2 ULCON3 0x5000C000 UART 3 line control U...

Page 69: ...040 0x0 W R Timer count observation 4 USB Device IR 0x4980_0000 0x0 R W Index Register EIR 0x4980_0004 0x0 R W Endpoint Interrupt Register EIER 0x4980_0008 0x0 R W Endpoint Interrupt Enable Register FAR 0x4980_000C 0x0 R Function Address Register EDR 0x4980_0014 0x0 R W Endpoint Direction Register TR 0x4980_0018 0x0 R W Test Register SSR 0x4980_001C 0x0 R W System Status Register SCR 0x4980_0020 0...

Page 70: ...er Watchdog Timer WTCON 0x53000000 0x0000_8021 W R W Watchdog timer mode WTDAT 0x53000004 0x0000_8000 Watchdog timer data WTCNT 0x53000008 0x0000_8000 Watchdog timer count IIC IICCON0 0x54000000 W R W IIC0 control IICSTAT0 0x54000004 IIC0 status IICADD0 0x54000008 IIC0 address IICDS0 0x5400000C IIC0 data shift IICLC0 0x54000010 IIC0 multi master line control IIS Multi Audio Interface IISCON 0x5500...

Page 71: ...ol G GPHCON 0x56000070 0x0 W R W Port H control GPHDAT 0x56000074 0x0 W R W Port H data GPHUDP 0x56000078 0x15555555 W R W Pull up down control H GPJCON 0x560000D0 0x0 W R W Port J control GPJDAT 0x560000D4 0x0 W R W Port J data GPJUDP 0x560000D8 0x55555555 W R W Pull up down control J GPJSEL 0x560000dc 0x0 W R W Selects the function of port J GPKCON 0x560000E0 0xAAAAAAAA W R W Port K control GPKD...

Page 72: ...R W Memory I F control register PDSMCON 0x56000118 0x05451500 W R W Memory I F control register RTC RTCCON 0x57000040 0x00 HW R W RTC control TICNT0 0x57000044 0x0 B R W Tick time count register 0 TICNT1 0x57000048 0x0 B R W Tick time count register 1 TICNT2 0x5700004C 0x0 W R W Tick time count register 2 RTCALM 0x57000050 0x0 B R W RTC alarm control ALMSEC 0x57000054 0x0 B R W Alarm second ALMMIN...

Page 73: ... 0x3 R W Feedback clock selecting register HSMMC Channel 0 SYSAD 0x4AC00000 0x00000000 W R W SDI control register BLKSIZE 0x4AC00004 0x00000000 HW R W Host DMA Buffer Boundary and Transfer Block Size Register BLKCNT 0x4AC00006 0x00000000 HW R W Blocks Count For Current Transfer ARGUMENT 0x4AC00008 0x00000000 HW R W Command Argument Register TRNMOD 0x4AC0000C 0x00000000 HW R W Transfer Mode Setting...

Page 74: ...rupt ADMAERR 0x4AC00054 0x00000000 W R W ADMA Error Status Register ADMASYSADDR 0x4AC00058 0x00000000 W R W ADMA System Address Register CONTROL2 0x4AC00080 0x00000000 W R W Control register 2 CONTROL3 0x4AC00084 0x7F5F3F1F W R W FIFO Interrupt Control Control Register 3 DEBUG 0x4AC00088 Not fixed W R W Debug register CONTROL4 0x4AC0008C 0x00000000 W R W HCVER 0x4AC000FE 0x00000401 HW HWInit Host ...

Page 75: ...PAREG 0x4A800040 0x05E80080 W HWInit Capabilities Register MAXCURR 0x4A800048 0x00000000 W HWInit Maximum Current Capabilities Register FEAER 0x4A800050 0x00000000 HW WO Force Event Auto CMD12 Error Interrupt Register Error Interrupt FEERR 0x4A800052 0x00000000 HW WO Force Event Error Interrupt Register Error Interrupt ADMAERR 0x4A800054 0x00000000 W R W ADMA Error Status Register ADMASYSADDR 0x4A...

Page 76: ...8100 W Command register for Line Point drawing CMD1_REG 0x4D408104 W Command register for BitBLT CMD2_REG 0x4D408108 W Command register for Host to Screen Bitblt transfer start CMD3_REG 0x4D40810C W Command register for Host to Screen Bitblt transfer continue CMD4_REG 0x4D408110 W Command register for Color Expansion Host to Screen Font Start CMD5_REG 0x4D408114 W Command register for Color Expans...

Page 77: ...0000 R W Rotation Origin Coordinates ROT_OC_X_REG 0x4D408344 0x0000_0000 R W X coordinate of Rotation Origin Coordinates ROT_OC_Y_REG 0x4D408348 0x0000_0000 R W Y coordinate of Rotation Origin Coordinates ROTATE_REG 0x4D40834C 0x0000_0001 R W Rotation Mode register X_INCR_REG 0x4D408400 0x0000_0000 R W X Increment register Y_INCR_REG 0x4D408404 0x0000_0000 R W Y Increment register ROP_REG 0x4D4084...

Page 78: ...ndian mode 2 The special registers have to be accessed for each recommended access unit 3 All registers except ADC registers RTC registers and UART registers must be read write in word unit 32 bit 4 Make sure that the ADC registers RTC registers and UART registers be read write by the specified access unit and the specified address 5 W 32 bit register which must be accessed by LDR STR or int type ...

Page 79: ...33MHz and 66MHz respectively Thus the power control of the ARM core is major issue to reduce the overall power dissipation in S3C2416 and IDLE mode is supported for this purpose In IDLE mode the ARM core is not operated until the external interrupts or internal interrupts The STOP mode freezes all clocks to all peripherals as well as the ARM core by disabling PLLs The power consumption is only due...

Page 80: ...rce and waits until external internal interrupts However the OFF part is disabled when the power down mode is SLEEP The clock generator makes all internal clocks which include ARMCLK for the ARM core HCLK for the AHB blocks PCLK for the APB block and other special clocks The special functional registers SFR are located at the register blocks and their values are configured through AHB interface If...

Page 81: ...erated Upon assertion of nRESET S3C2416 enters reset state regardless of the previous state To enter hardware reset state nRESET must be held long enough to allow internal stabilization and propagation of the reset state Caution An external power source regulator for S3C2416 must be stable prior to the deassertion of nRESET Otherwise it damages to S3C2416 and its operation will not be guaranteed F...

Page 82: ...ts except some blocks listed in table 2 1 go into their pre defined reset state All pins get their reset state and BATT_FLT pin is ignored The nRSTOUT pin is asserted during watchdog reset Watchdog reset can be activated in normal and idle mode because watchdog timer can expire with clock Watchdog reset is invoked when watchdog timer and reset are enabled WTCON 5 1 WTCON 0 1 and watchdog timer is ...

Page 83: ...lf refresh mode 5 System controller wait for self refresh acknowledge from memory controller 6 Internal reset signals and nRSTOUT are asserted and reset counter is activated 7 Reset counter is expired then internal reset signals and nRSTOUT are deasserted 4 5 WAKEUP RESET When S3C2416 is woken up from SLEEP mode by wakeup event the wakeup reset is invoked The detail description will be explained i...

Page 84: ... clock source can be reference of PLL after oscillated at PAD User can configure stabilization time by setting OSCSET register and ON OFF when power down mode by setting PWRCFG register The clock generator consists of two PLLs Phase Locked Loop which generate the high frequency clock signals required in S3C2416 MPLL ExtClk Div XTI EXTCLK OM 0 ARMCLK HCLK PCLK DDRCLK SYSCLK EPLL XTI EXTCLK ECLK USB...

Page 85: ...ock 0 X 0 XTI 0 X 1 EXTCLK 1 0 X XTI 1 1 X EXTCLK Table 2 4 PLL Clock Generator Condition MPLLCAP N A Loop filter capacitance CLF EPLLCAP Typical 1 8nF 5 Fin MPLL 10 30 MHz EPLL 10 40 MHz Fout MPLL 40 1600 MHz EPLL 20 600 MHz External capacitance used for X tal CEXT 15 pF Feedback Resistor used for X tal RF 1MΩ Figure 2 4 Main Oscillator Circuit Examples ...

Page 86: ... Refer to MPLLCON and EPLLCON registers to change PLL output frequency Fout Off chip loop filter Fin Pre Divider Main Divider PFD Charge Pump VCO Post Scaler Figure 2 5 PLL Phase Locked Loop Block Diagram 5 4 CHANGE PLL SETTINGS IN NORMAL OPERATION During the operation of S3C2416 in NORMAL mode if the user wants to change the frequency by writing the PMS value the PLL lock time is automatically in...

Page 87: ...wer down controller and etc The PCLK is used for internal APB bus and peripherals such as WDT IIS I2C PWM timer ADC UART GPIO RTC and SPI etc DDRCLK is the data strobe clock for mDDR DDR2 memories CAMclk is used for camera interface block HCLKCON and PCLKCON registers are used for clock gating of HCLK PCLK respectively SCLKCON register is responsible for EPLLclk clock gating on related modules Fig...

Page 88: ...e 2 5 shows that DDRCLK PCLK ARMCLK divide ratio with regard HCLK ratio The fraction in the cell is ratio to MSysClk and the value in the round bracket means maximum frequency value Table 2 5 Clock Division Ratio of MPLL Region MSysClk 800MHz HCLK 133MHz DDRCLK 266MHz PCLK SSMC 133MHz ARMCLK 400MHz 1 1 1 1 1 1 or 1 2 1 1 1 2 1 1 1 2 or 1 4 1 1 or 1 2 1 3 1 1 1 3 or 1 6 1 1 or 1 3 1 4 1 2 1 4 or 1 ...

Page 89: ...0MHz Target frqeuency ARMCLK 400MHz HCLK 133MHz PCLK 66MHz DDRCLK 266MHz SSMCCLK 66MHz Register value ARMDIV 4 b0001 PREDIV 2 b10 HCLKDIV 2 b01 PCLKDIV 1 b1 HALKHCLK 1 b1 When PLL output frequency 533MHz Target frqeuency ARMCLK 266MHz HCLK 133MHz PCLK 66MHz DDRCLK 266MHz SSMCCLK 66MHz Register value ARMDIV 4 b0001 PREDIV 2 b01 HCLKDIV 2 b01 PCLKDIV 1 b1 HALKHCLK 1 b1 ...

Page 90: ... SCLKCON register According to USB host interface If you want to get the clock with exact 50 duty cycle then make EPLL generate 96MHz and divide the clock EPLL will be turned off during STOP and SLEEP mode automatically Also EPLL will be generated clock to ESYSCLK after exiting STOP and SLEEP mode if corresponding bits are enabled in SCLKCON register Table 2 6 ESYSCLK Control Condition ESYSCLK sta...

Page 91: ...ur power down modes The following section describes each power management mode Related registers are PWRMODE PWRCFG and WKUPSTAT 6 1 POWER MODE STATE DIAGRAM Figure 2 10 shows that Power Saving mode state and Entering or Exiting condition In general the entering conditions are set by the main CPU Normal General Clock Gating Mode IDLE SLEEP STOP or DEEP STOP STANDBYWFI CMD CMD One of wakeup source ...

Page 92: ... and oscillator circuit are also stopped oscillator circuit is stopped optionally see PWRCFG register The STOP Mode is activated after the execution of the STORE instruction that enables the STOP Mode bit The STOP Mode bit should be cleared after the wake up from the STOP state for the entering of next STOP Mode The H W logic only detects the low to high triggering of the STOP Mode bit In Deep STO...

Page 93: ...abled ARM_PWRENn signal change to enable ARM power gating ARM Core is reset state during STOP mode STOP mode Exiting sequence is as follows 1 Enable X tal Oscillator if it is used and wait the OSC settle down around 1ms 2 After the Oscillator settle down the System Clock is fed using the PLL input clock and also enable the PLLs and waits the PLL locking time 3 Switching the clock source now the PL...

Page 94: ...contents in SDRAM 7 System controller wait for self refresh acknowledge from memory controller 8 After receiving the self refresh acknowledge System controller disable system clocks HCLK PCLK and so on 9 System controller asserts control signals to mask unknown state of ALIVE logics and to preserve data of retention Pads 10 System controller asserts PWR_EN pin and disables the X tal and PLL oscill...

Page 95: ...S3C2416X RISC MICROPROCESSOR SYSTEM CONTROLLER 2 17 a Figure 2 11 Entering STOP Mode and Exiting STOP Mode wake up ...

Page 96: ...C2416X RISC MICROPROCESSOR 2 18 Wake up event ARM Down Req Ack ARMCLK SYSCLK DRAM Self Refresh Req Ack PWR_EN SLEEP mode is initiated CKE DRAM BUS Down Req Ack Figure 2 12 Entering SLEEP Mode and Exiting SLEEP Mode wake up ...

Page 97: ...us working state after wake up from the STOP Mode The following table shows the states of PLLs and internal clocks after wake ups from the power saving modes Table 2 7 The Status of PLL and ARMCLK After Wake up Mode before wake up PLL on off after wake up SYSCLK after wake up and before the lock time SYSCLK after the lock time by internal logic IDLE Unchanged PLL output PLL output STOP PLL state a...

Page 98: ...enter sleep mode by BATT_FLT you have to configure BATF_CFG bits of PWRCFG register Not to exit from sleep mode when BATT_FLT is LOW you have to configure SLEEP_CFG bit of PWRCFG register Table 2 8 Power Saving Mode Entering Exiting Condition Power down mode Enter Exit Clock Gating at NORMAL Clear a respective clock on off bit for each IP to save power Set a respective clock on off bit for each IP...

Page 99: ...trol register1 X 0x0000_0000 CLKDIV2 0x4C00_002C R W Clock divider ratio control register2 X 0x0000_0000 HCLKCON 0x4C00_0030 R W HCLK enable register X 0xFFFF_FFFF PCLKCON 0x4C00_0034 R W PCLK enable register X 0xFFFF_FFFF SCLKCON 0x4C00_0038 R W Special clock enable register X 0xFFFF_DFFF PWRMODE 0x4C00_0040 R W Power mode control register X 0x0000_0000 SWRST 0x4C00_0044 R W Software reset contro...

Page 100: ...4C00_001C R W EPLL configuration register for K value 0x0000_0000 Conventional PLL requires stabilization duration after the PLL is ON The duration can be varied according to the device variation Thus software must adjust these fields with appropriate values in the LOCKCON0 1 register whose values mean the number of the external reference clock LOCKCON0 Bit Description Initial Value RESERVED 31 16...

Page 101: ...ollowing equations FOUT m x FIN p x 2S should be 40 1600MHz Fvco m x FIN p should be 800 1600MHz where m MDIV p PDIV s SDIV Fin 10 30Mhz Don t set the value PDIV 5 0 or MDIV 9 0 to all zeros 6 b00 0000 10 b00 0000 0000 NOTE Although there is the equation for choosing PLL value we strongly recommend only the values in the PLL value recommendation table If you have to use other values please contact...

Page 102: ...tor 0x0000 The output frequencies of EPLL can be calculated using the following equations FOUT m k 216 FIN p 2 s should be 20 600MHz Fvco m x FIN p where m MDIV p PDIV s SDIV k KDIV Fin 10 40MHz Don t set the value PDIV 5 0 or MDIV 7 0 to all zeros 6 b00 0000 8 b0000 0000 NOTE Although there is the equation for choosing PLL value we strongly recommend only the values in the PLL value recommendatio...

Page 103: ...egister Address R W Description Reset Value CLKSRC 0x4C00_0020 R W Clock source control register 0x0000_0000 CLKDIV0 0x4C00_0024 R W Clock divider ratio control register0 0x0000_000C CLKDIV1 0x4C00_0028 R W Clock divider ratio control register1 0x0000_0000 CLKDIV2 0x4C00_002C R W Clock divider ratio control register2 0x0000_0000 HCLKCON 0x4C00_0030 R W HCLK enable register 0xFFFF_FFFF PCLKCON 0x4C...

Page 104: ...0 SELESRC 8 7 Selection EPLL reference clock 10 XTAL 11 EXTCLK 0x identical to that of MPLL reference clock Do not configure SELESRC SELEPLL register simultaneously 00 SELEPLL 6 EsysClk selection 0 EPLL reference clock 1 EPLL output 0 RESERVED 5 0 SELMPLL 4 MSYSCLK selection 0 MPLL reference clock produced through clock divider 1 MPLL output 0 SELEXTCLK 3 Configure MPLL reference clock divider 0 d...

Page 105: ...b001 1 3 3 b010 1 4 3 b011 1 6 3 b101 1 8 3 b111 0x0 EXTDIV 8 6 External clock divider ratio ratio MPLL reference clock EXTDIV 2 1 0 PREDIV 5 4 Pre Divider for HCLK PREDIV value should be one of 0 1 2 3 Output frequency of PREDIVIDER should be less than 266MHz 0 HALFHCLK 3 HCLKx1_2 SSMC clock divider ratio 0 HCLK 1 HCLK 2 User also has to configure SSMC s special register which related with half c...

Page 106: ... clock divider ratio ratio I2SDIV_0 1 0x0 UARTDIV 11 8 UART clock divider ratio ratio UARTDIV 1 0x0 HSMMCDIV_1 7 6 HSMMC_1 clock divider ratio ratio HSMMCDIV_1 1 0x0 USBHOSTDIV 5 4 Usb Host clock divider ratio ratio USBHOSTDIV 1 0x0 RESERVED 3 0 0 CLKDIV2 configures the clock ratio related on EPLL or MPLL CLKDIV2 Bit Description Initial Value RESERVED 31 8 0 HSMMCDIV_0 7 6 HSMMC_0 clock divider ra...

Page 107: ...e 1 USBHOST 11 Enable HCLK into the USB HOST 1 RESERVED 10 1 DISPCON 9 Enable HCLK into the display controller 1 RESERVED 8 6 0x3 DMA0 5 7 0 Enable HCLK into DMA channel 0 5 0x3F PCLKCON Bit Description Initial Value RESERVED 31 20 0xFFF PCM 19 Enable PCLK into the PCM 1 RESERVED 18 14 0x1F GPIO 13 Enable PCLK into the GPIO 1 RTC 12 Enable PCLK into the RTC 1 WDT 11 Enable PCLK into the watch dog ...

Page 108: ...ESERVED 18 1 PCM0_EXT 17 Enable PCM0 External Clock 1 DDRCLK Hx2CLK 16 Enable DDRCLK 1 SSMCCLK HX1_2CLK 15 Enable SSMCCLK 1 SPICLK_0 14 Enable HS SPI_0 EPLL clock 1 HSMMCCLK_EXT 13 Enable HSMMC_EXT clock for HSMMC0 1 EXTCLK Reference clock of MPLL 0 HSMMCCLK_1 12 Enable HSMMC1_1 clock for from EPLL or USB48M output 1 RESERVED 11 1 DISPCLK 10 Enable display controller clock 1 I2SCLK_0 9 Enable I2S_...

Page 109: ...eld is set to 1 0 SLEEP 15 0 The system enters into SLEEP mode when this field is set to 0x2BED The bit pattern 0x2BED represents Go To BED 0 PWRCFG register controls the configuration of power mode transition PWRCFG Bit Description Initial Value RESERVED 31 18 0x0000 STANDBYWFI_EN 17 Enable entering of IDLE mode by STANDBYWFI 0 Disable 1 Enable 0 DEEP STOP 16 Enable the system enters DEEP STOP mo...

Page 110: ...rupt 0 RESERVED 6 5 These bits must be 0b 00 0 nSW_PHY_ OFF_USB 4 Power on off of USB PHY See USB manual to get more details 0 OFF 1 ON 0 OSC_EN_SLP 3 Crystal oscillator enable bit in SLEEP mode 0 Disable in SLEEP mode 1 Enable in SLEEP mode 0 OSC_EN_STOP 2 Crystal oscillator enable bit in STOP mode 0 Disable in STOP mode 1 Enable in STOP mode 0 BATF_CFG 1 0 Configure BATT_FLT operation 00 10 Igno...

Page 111: ...0x3 0x3 PWROFF_SLP 16 Power Control on pad retention cell I O Retention cell I O s power will be off when sleep mode but when wakeup process starts User should write 1 to produce power on retention I O see below detailed description 1 set automatically when sleep mode 0 cleared by user writing 1 0 RSTCNT 15 8 Only watch dog and software reset can start counter which is counted from RSTCNT value Th...

Page 112: ...tput of level shifter cannot pass therefore retention PAD produces latched data only When the system enters into a sleep mode SLP_IN value has HIGH value as a result of PWROFF s HIGH state Futhermore PWROFF_SLP register bit is automatically set to 1 b1 When the system wakeup from sleep mode SLP_IN still remains HIGH state until user configure PWROFF_SLP bit as 1 b0 Therfore user has to configure P...

Page 113: ...ESET WDTRST SLEEP DEEP STOP SW Reset RSTSTAT Bit Description Initial Value RESERVED 31 6 0x0000_000 SWRST 5 Reset by software see SWRST register 0 DEEP STOP 4 Wakeup from DEEP STOP ARM Reset only 0 SLEEP 3 Wakeup from RTC_TICK RTC_ALARM EINT and battery fault from power down mode Reset by waking up from SLEEP mode 0 WDTRST 2 Reset by Watch dog reset 0 RESERVED 1 0 EXTRST 0 External reset by nRESET...

Page 114: ...tated type 4 2 b11 undefined BUSPRI0 Bit Description Initial Value RESERVED 31 16 0x0000 TYPE_S 15 14 Priority type for AHB System bus 0x0 RESERVED 13 12 0x0 ORDER_S 11 8 Fixed priority order for AHB S bus Value Priority Value Priority 4 h0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 4 h8 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 4 h1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 4 h9 9 10 11 12 13 14 15 0 1 2 3 4 ...

Page 115: ... 0 1 2 3 Register Address R W Description Reset Value INFORM0 0x4C00_0070 R W SLEEP mode information register 0 0x0000_0000 INFORM1 0x4C00_0074 R W SLEEP mode information register 1 0x0000_0000 INFORM2 0x4C00_0078 R W SLEEP mode information register 2 0x0000_0000 INFORM3 0x4C00_007C R W SLEEP mode information register 3 0x0000_0000 INFORM0 3 registers retain their contents during SLEEP mode Thus i...

Page 116: ...2 When Combination of 5 2 bit is 2 b11 could be off clock input 00 Crystal Enable 01 Oscillator Enable 11 Crystal Oscillator Disable PAD Disable 10 reserved 0 CLK_SEL 4 3 Reference Clock Frequency Select 00 48MHz 01 Reserved 10 12MHz 11 24MHz 2 b00 EXT_CLK 2 Clock Select 0 Crystal 1 Oscillator 0 INT_PLL_SEL 1 Host 1 1 uses which PLL Clock 48MHz 0 use EPLL USBHOSTCLK should be 48MHz and The CLK_SEL...

Page 117: ...RESERVED 3 1 Must be zero 2 b000 FORCE_ SUSPEND 0 Apply Suspend signal for power save 0 Disable Normal Operation 1 Enable 0 8 11 USB RESET CONTROL REGISTER URSTCON Register Address R W Description Reset Value URSTCON 0x4C00_0088 R W USB Reset Control Register 0x0000_0000 URSTCON Bit Description Initial State RESERVED 31 3 0 FUNC_RESET 2 Function 2 0 S W Reset 1 Reset 0 HOST_RESET 1 Host 1 1 S W Re...

Page 118: ...his VBUS indicator signal indicates that the VBUS signal on the USB cable is active For the serial interface this signal controls the pull up resistance on the D line in Device mode only 1 Pull up resistance on the D line is enabled based on the speed of operation 0 Pull up resistance on the D line is disabled 0 RESERVED 30 3 0 FUNC_CLK_EN 2 USB 2 0 Function Clock Enable 0 Disable 1 Enable 0 HOST_...

Page 119: ...ent AHB bus one is for system and the other is for image at the same time S3C2416 have two MATRIX cores because it has two memory ports and each MATRIX can select the priority between rotation type and fixed type User can select which one is excellent for improving system performance Matrix Memory Controller EBI AHB S AHB I SFR MATRIX CORE0 MATRIX CORE1 SSMC NFCON DRAMC EBI External Memory SROM NF...

Page 120: ...ate PRI_TYP 2 Priority type 0 Fixed Type 1 Rotation Type 1 FIX_PRI_TYP 0 Priority for the fixed priority type 0 AHB_S AHB_I 1 AHB_I AHB_S 0 2 2 MATRIX CORE 1 PRIORITY REGISTER BPRIORITY1 Register Address R W Description Reset Value BPRIORITY1 0X4E800004 R W Matrix Core 1 priority control register 0x0000_0004 BPRIORITY1 Bit Description Initial State PRI_TYP 2 Priority type 0 Fixed Type 1 Rotation T...

Page 121: ... EBI control register 0x0000_0004 EBICON Bit Description Initial State Reserved 31 9 Should be 0 0 BANK1_CFG 8 Bank1 Configuration 0 SROM 1 NAND 0 PRI_TYP 2 Priority type 0 Fixed Type 1 Rotation Type 1 FIX_PRI_TYP 1 0 Priority for the fixed priority type 2b 0X SSMC NFCON ExtBusMaster 2b 10 SSMC ExtBusMaster NFCON 2b 11 ExtBusMaster SSMC NFCON 00 ...

Page 122: ...BUS MATRIX EBI S3C2416X RISC MICROPROCESSOR 3 4 NOTES ...

Page 123: ...ters on the APB Bus The following list shows the priorities among these bus masters after a reset Priority AHB_S BUS MASTERS Comment 0 Reserved 1 HS MMC1 2 DMA0 3 DMA1 4 DMA2 5 DMA3 6 DMA4 7 DMA5 8 Reserved 9 Reserved 10 UHOST 11 UDEVICE20 12 HS MMC0 13 ARM926EJ DBUS 14 ARM926EJ IBUS 15 Default 1 Fix Type all priority can be changed according to register value stored in The System Controller 2 Rot...

Page 124: ... according to register value stored in The System Controller 2 Rotation Type all masters priority can be rotatable according to register value stored in The System Controller except for Default Master Priority APB BUS MASTERS Comment 0 AHB2APB 1 DMA0 2 DMA1 3 DMA2 4 DMA3 5 DMA4 6 DMA5 7 Reserved 8 Reserved AHB2APB Bridge Master obtains always highest priority and the priority of six DMA channels r...

Page 125: ...D You can configure each memory bank to use 8 or 16 bit external memory data paths You can configure the SMC to support either little endian or big endian operation For example each memory bank can be configured to support nonburst read and write accesses to high speed CMOS asynchronous static RAM nonburst write accesses nonburst read accesses and asynchronous page mode read accesses to fast boot ...

Page 126: ...d the bus cycle Support byte half word and word access for external memory Programmable wait states up to 31 Programmable bus turnaround cycles up to 15 Programmable output enable and write enable delays up to 15 Configurable size at reset for boot memory bank using external control pins Support for interfacing to another memory controller using an External Bus Interface EBI Multiple memory clock ...

Page 127: ... Interface AHB Slave Interface Figure 5 1 SMC Block Diagram AHB Slave Interface for Register Access AHB Slave Interface for Memory Access Transfer State Machine Control Signals Control Signals Synchronizer Module nWAIT SMCANCELWAIT Pad Interface Block Control Signals AHB I F for SMC SFR AHB I F for SMC MEM SRAM MEM I F SMBUSGNTEBI SMBUSREQEBI Figure 5 2 SMC Core Block Diagram ...

Page 128: ...ht be required for synchronous static memory devieces when you use it in asynchronous mode You can disable this using the AddrValidReadEn bit in the SMBCRx register This bit defaults to being set enable to enable a system to boot from synchronous memory You can then clear it if you do not require it When disabled the signal is driven HIGH continuously SMCLK ADDR DATA IN Asynchronous Read nCS nOE A...

Page 129: ...S3C2416X RISC MICROPROCESSOR STATIC MEMORY CONTROLLER 5 5 SMCLK ADDR DATA R nCS nWAIT A D A nOE Figure 5 5 Read Timing Diagram DRnCS 1 DRnOWE 1 ...

Page 130: ...e address changes between subsequent accesses At the end of the burst the chip select and output enable lines are deasserted together Asynchronous page mode read operation is supported This is enabled by setting the BMRead bit and by setting the burst length using BurstLenRead in the SMBCRx register Sequential bursts of up to four or eight beats are the only type of access supported for page mode ...

Page 131: ...nous burst reads because of the internal address incrementing performed by synchronous burst devices The PADDR outputs are held with the initial address value and the PSMAVD output is asserted during the transfer to indicate that the address is valid Four eight or continuous synchronous burst lengths are supported and are controlled by the BurstLenRead bits in the Bank Control Register SMBCRx when...

Page 132: ...N for writes to 8 bit devices that use the byte lane selects instead of the write enables The WSTWEN programmed value must be equal to or less than the WSTWR programmed value otherwise an invalid access sequence is generated The access is timed by the WSTWR value and not by the WSTWEN value In the External Wait enabled mode the timing of the transfer controlled by SMWAIT is not known WSTWEN still ...

Page 133: ...ICROPROCESSOR STATIC MEMORY CONTROLLER 5 9 SMCLK ADDR DATA W D A nCS nWE A nWAIT Figure 5 9 Write Timing Diagram DRnCS 1 DRnOWE 0 SMCLK ADDR DATA W D A nCS nWE A nWAIT Figure 5 10 Write Timing Diagram DRnCS 1 DRnOWE 1 ...

Page 134: ...nWE is only active for one cycle This is active at the start of the transfer unless it is delayed using the control bits WSTWEN to delay it Synchronous burst writes are supported by the SMC There is no write buffer so you must delay the AHB transfer to enable the data to be output onto the SMDATA bus You can control the write in the same way as reads using the bits AddrValidWriteEn BurstLenWrite S...

Page 135: ...rite to different memory banks Figure 5 12 shows a zero wait asynchronous read followed by two zero wait asynchronous writes with two turnaround cycles added The standard minimum of two AHB wait states are added to the read transfer one is added to the first write as for any read write transfer sequence and three are added to the second write because of insertion of the two turnaround cycles that ...

Page 136: ...STATIC MEMORY CONTROLLER S3C2416X RISC MICROPROCESSOR 5 12 3 6 1 Scenario Examples ADDR CS 3 cycle CS OE 4 cycle CS WE 5 cycle ...

Page 137: ...EMORY CONTROLLER 5 13 3 6 2 SRAM Memory Interface Examples Figure 5 13 Memory Interface with 8 bit SRAM 2MB Figure 5 14 Memory Interface with 16 bit SRAM 4MB SRAM ROM S3C2416 8bit data bus A0 RADDR0 Addr connection 16bit data bus A0 RADDR0 ...

Page 138: ...tention on the external memory data bus Turnaround time IDCY x SMCLK period 0xF 4 2 BANK READ WAIT STATE CONTROL REGISTERS 0 5 Register Address R W Description Reset Value SMBWSTRDR0 0x4F000004 R W Bank0 read wait state control register 0x1F SMBWSTRDR1 0x4F000024 R W Bank1 read wait state control register 0x1F SMBWSTRDR2 0x4F000044 R W Bank2 read wait state control register 0x1F SMBWSTRDR3 0x4F000...

Page 139: ... wait assertion timing for writes Wait state time WSTWR x SMCLK period WSTWR does not apply to read only devices such as ROM 0x1F 4 4 BANK OUTPUT ENABLE ASSERTION DELAY CONTROL REGISTERS 0 5 Register Address R W Description Reset Value SMBWSTOENR0 0x4F00000C R W Bank0 output enable assertion delay control register 0x2 SMBWSTOENR1 0x4F00002C R W Bank1 output enable assertion delay control register ...

Page 140: ...k3 write enable assertion delay control register 0x2 SMBWSTWENR4 0x4F000090 R W Bank4 write enable assertion delay control register 0x2 SMBWSTWENR5 0x4F0000B 0 R W Bank5 write enable assertion delay control register 0x2 Bit Description Initial State 31 4 Read undefined Write as zero 0x0 WSTWEN 3 0 Write enable assertion delay from chip select assertion Default to 0x2 at reset 0x2 NOTE SMBWSTRDRx S...

Page 141: ...gnal active for asynchronous and synchronous write accesses default 0x1 BurstLenWrite 19 18 Burst transfer length Sets the number of sequential transfers that the burst device supports for a write 00 4 transfer burst default 01 Reserved 10 Reserved 11 Reserved 0x0 SyncWriteDev 17 0 Asynchronous device default 1 Synchronous device 0x0 BMWrite 16 Burst mode write 0 Nonburst writes to memory devices ...

Page 142: ... for each bank For SMBCR0 reset value is set according to OM See table 1 4 See note in p5 17 Reserved 3 Reserved 0x0 WaitEn 2 External memory controller wait signal enable 0 The SMC is not controlled by the external wait signal default at reset 1 The SMC looks for the external wait input signal nWAIT 0x0 WaitPol 1 Polarity of the external wait input for activation 0 The nWAIT signal is active LOW ...

Page 143: ... MUXED OneNAND 0x0 BANK2TYPE 2 0 DEMUXED OneNAND 1 MUXED OneNAND 0x0 BANK1TYPE 1 0 DEMUXED OneNAND 1 MUXED OneNAND 0x0 0 Reserved 0x0 NOTE Type of bank0 OneNAND is determined by OM 4 2 signals See table 1 4 4 8 SMC STATUS REGISTER Register Address R W Description Reset Value SMCSR 0x4F000200 R SMC status register 0x0 Bit Description Initial State 31 1 Read undefined 0x0 WaitStatus 0 External wait ...

Page 144: ...K 0 SMCLK HCLK 1 SMCLK HCLK 2 0x1 SMClockEn 0 SMCLK enable 0 Clock only active during memory accesses 1 Clock always running Clock stopping saves power by stopping SMCLK when it is not required If clock stopping is enabled before the memory access the SMC stops SMCLK on the following conditions asynchronous read access to asynchronous memory asynchronous write access to asynchronous memory asynchr...

Page 145: ...ttle endian Mobile DDR SDRAM and Mobile SDRAM Supports 32 bit for SDRAM and 16 bit data bus interface for mDDR and DDR2 Address space up to 128Mbyte Supports 2 banks 2 nCS chip selection 16 bit Refresh Timer Self Refresh Mode support controlled by power management Programmable CAS Latency Provide Write buffer 8 word size Provide pre charge and active power down mode Provide power save mode Support...

Page 146: ...MOBILE DRAM CONTROLLER S3C2416X RISC MICROPROCESSOR 6 2 2 BLOCK DIAGRAM Follow Figure 6 1 shows the block diagram of Mobile DRAM Controller Figure 6 1 Mobile DRAM Controller Block Diagram ...

Page 147: ...RS command to the Mobile DRAM It s only needed for Mobile DRAM 10 Program the INIT 1 0 to 00b The controller enters the normal mode 11 The external DRAM is now ready for normal operation 3 2 DDR2 INITIALIZATION SEQUENCE 1 Setting the BANKCFG BANKCON1 2 3 2 Wait 200us to allow DRAM power and clock stabilize 3 Wait minimum of 400 ns then issue a PALL pre charge all command Program the INIT 1 0 to 01...

Page 148: ...17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 BA0 BA1 LDQM UDQM A14 A15 DQM0 DQM1 SCKE SCLK SCKE SCLK nSCS0 nSRASn SCASn WE nSCS nSRAS nSCAS nWE A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A0 A...

Page 149: ...A14 A15 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 BA0 BA1 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 LDQM UDQM DQS0 DQS1 DQM0 DQM1 DQS0 DQS1 SCKE SCLK SCLKn CKE CK nCK nSCS0 nSRASn SCASn WE nSCS nSRAS nSCAS nWE Figure 6 4 Memory Interface with 16 bit Mobile DDR and DDR2 ...

Page 150: ...provided by DRAM And DRAMC only provides some timing parameters to support various DRAM memories like SDR mobile DDR and DDR2 tARFC and tRP are programmable so you can also control the tRAS period by using these parameters And the delay from RAS to CAS is determined by tRCD And CL CAS Latency is also programmable The timing diagram of CL CAS Latency is like Figure 6 6 Figure 6 6 CL CAS Latency Tim...

Page 151: ...OR MOBILE DRAM CONTROLLER 6 7 DRAMC also needs tARFC timing parameter to control of the timing for auto refresh to CMD and self refresh to CMD period The Figure 6 7 shows the tARFC timing diagram Figure 6 7 tARFC Timing Diagram ...

Page 152: ...bit width of RAS row address of bank 1 00 11 bit 01 12 bit 10 13 bit 11 14 bit 00b Reserved 13 Reserved 0b CASBW0 12 11 The bit width of CAS column address of bank 0 00 8 bit 01 9 bit 10 10 bit 11 11 bit 00b Reserved 10 Reserved 0b CASBW1 9 8 The bit width of CAS column address of bank 1 00 8 bit 01 9 bit 10 10 bit 11 11 bit 00b ADDRCFG0 7 6 Memory address configuration of 00 BA RAS CAS 01 RAS BA ...

Page 153: ...port Read Burst Stop 1 Support Read Burst Stop Note This function is only valid in mDDR interface 0b WBUF 6 Write buffer control 0 Disable 1 Enable Note Disabling the write buffer will flush any stored values to the external DRAM memory 1b AP 5 Auto pre charge control 0 Enable auto pre charge 1 Disable auto pre charge Note If PWRDN is enabled then AP 0 provides pre charge power down and AP 1 provi...

Page 154: ...ock1010 11 clock1011 12 clock 1100 13 clock1101 14 clock1110 15 clock1111 16 clock 1001b tARFC 19 16 Self refresh or Auto refresh to next command cycle time 0000 1 clock 0001 2 clock 0010 3 clock 0011 4 clock 0100 5 clock 0101 6 clock 0110 7 clock 0111 8 clock 1000 9 clock 1001 10 clock1010 11 clock1011 12 clock 1100 13 clock1101 14 clock1110 15 clock1111 16 clock 1001b Reserved 15 6 Reserved 0x00...

Page 155: ...be 0 00b PASR 18 16 PASR Partial Array Self Refresh for EMRS 000b BA 15 14 Bank address for MRS 0b Reserved 15 7 Should be 0 000000000b CAS Latency 6 4 CAS Latency for MRS 00 Reserved 01 1 clock 10 2 clock 11 3 clock 000b Burst Type 3 DRAM Burst Type Read Only Only support sequential burst type 0b Burst Length 2 0 DRAM Burst Length Read Only This value is determined internally 011b NOTE Bit 15 0 i...

Page 156: ...er to DDR2 spec 000b Rtt 22 18 00 ODT disable 01 75Ω 10 150Ω 11 50Ω 00b D I C 17 0 Full strength 1 Reduced strength 0b DLL enable 16 0 Enable 1 Disable 0b Reserved 15 13 Should be 0 000b Active Power down exit time 12 0 Fast exit 1 Slow exit 0b WR 11 9 Write recovery for auto pre charge 000b DLL Reset 8 0 No 1 Yes 0b TM 7 0 Normal 1 Test 0b CAS Latency 6 4 CAS Latency for MRS 00 Reserved 01 1 cloc...

Page 157: ... Reserved 29 24 Should be 0 000000b SRF 23 High Temperature Self Refresh Rate Enable 0 Disable 1 Enable 0b Reserved 22 20 Should be 0 000b DCC 19 0 Disable 1 Enable 0b PASR 18 16 PASR Partial Array Self Refresh for EMRS 2 000b 3 6 4 DDR2 Memory EMRS 3 31 16 PnBANKCON Bit Description Initial State BA 31 30 Bank address for EMRS 10b Reserved 29 16 Should be 0 0x0 ...

Page 158: ...1029 0x0020 3 8 MOBILE DRAM WRITE BUFFER TIME OUT REGISTER A write to a enabling write buffer loads the value in the timeout register into timeout down counter of the buffer When the timeout counter reached 0 the contents of write buffer is flushed to the external DRAM The down counter is clocked HCLK Writing a value of 0 in the TIMEOUT register disables the write buffer timeout function Register ...

Page 159: ...evice in IROM boot Refer to IROM application Note for more information S3C2416 supports nand boot by using IROM boot mode 2 FEATURES NAND flash controller features include 1 Auto boot by The boot code is transferred into 8 KB Steppingstone after reset After the boot code is transfered boot code will be executed on the Steppingstone Note IROM boot support 8Bit ECC correction on Nand device booting ...

Page 160: ...T CORE ACCESS Boot Code USER ACCESS Figure 7 2 NAND Flash Controller Boot Loader Block Diagram During reset the IROM gets the information about the adopted NAND flash memory by using the pin status of GPC5 6 7 refer to Pin Configuration In case of POR Power On Reset or system reset the IROM automatically loads the 8 KB boot loader codes into the steppingstone 0x40000000 After finishing the migrati...

Page 161: ...96 5 1 1 0 Above configuration is applicable when NAND Flash is used as booting memory in IROM boot mode If NAND Flash is not used as boot memory the configuration can be changed by setting NFCON SFR NFCONF 0x4E000000 PageSize PageSize_Ext and AddrCycle are fields in NFCONF 0x4E000000 6 NAND FLASH MEMORY TIMING HCLK CLE ALE nWE TACLS TWRPH0 TWRPH1 DATA COMMAND ADDRESS Figure 7 3 CLE ALE Timing TAC...

Page 162: ...mory correctly 1 Writing to the command register NFCMMD the NAND Flash Memory command cycle 2 Writing to the address register NFADDR the NAND Flash Memory address cycle 3 Writing to the data register NFDATA write data to the NAND Flash Memory write cycle 4 Reading from the data register NFDATA read data from the NAND Flash Memory read cycle 5 Reading main ECC registers and Spare ECC registers NFME...

Page 163: ...his area for various other purpose 10 1BIT 4BIT 8BIT ECC ERROR CORRECTION CODE NAND flash controller has four ECC Error Correction Code modules for 1 bit ECC one for 4bit ECC and one for 8bit ECC The 1bit ECC modules for main data area can be used for up to 2048 bytes ECC parity code generation and 1 bit ECC module for spare area can be used for up to 4 bytes ECC Parity code generation Both 4bit a...

Page 164: ...ECC data read from memory must be written to NFMECCDn for main area and NFSECCD for spare area NOTE 4 bit ECC decoding scheme is different to 1 bit ECC 1 NAND Flash Memory Interface Register Bit 31 24 Bit 23 16 Bit 15 8 Bit 7 0 NFMECCD0 Not used 2nd ECC for I O 7 0 Not used 1st ECC for I O 7 0 NFMECCD1 Not used 4th ECC for I O 7 0 Not used 3rd ECC for I O 7 0 Register Bit 31 24 Bit 23 16 Bit 15 8 ...

Page 165: ...rom main data area to Spare area which value will be the same as NFMECC0 1 10 3 4 BIT ECC PROGRAMMING GUIDE ENCODING 1 To use 4 bit ECC in software mode set the MsgLength to 0 512 byte message length and set the ECCType to 1 enable 4 bit ECC ECC module generates ECC parity code for 512 byte write data So you have to reset ECC value by writing the InitMECC NFCONT 5 bit as 1 and have to clear the Ma...

Page 166: ...r not 7 Whenever data is read the 4 bit ECC module generates ECC parity code internally 8 After you complete read 24 byte you have to read parity codes 4 bit ECC module needs parity codes to detect whether error bits are or not So you have to read ECC parity codes right after read 24 byte Once ECC parity code is read 4 bit ECC engine start to search any error internally 4 bit ECC error searching e...

Page 167: ...So you have to read the ECC parity code of 512 byte main data right after reading the 512 byte data Once the ECC parity code is read 8bit ECC engine starts searching any error internally 8bit ECC error searching engine needs minimum 372 cycles to find any error During this time you can continue reading data from external NAND flash memory ECCDecDone NFSTAT 6 can be used to check whether ECC decodi...

Page 168: ...CS3 SROM nRCS2 SROM nRCS1 SROM nRCS0 Using OneNAND for boot ROM SRAM 8KB SDRAM nSCS1 SDRAM nSCS0 SROM nRCS5 SROM nRCS4 ROM nRCS3 SROM nRCS2 SROM nRCS1 Internal iROM Using iROM for boot ROM MPORT1 MPORT0 0x1800_0000 0x0000_0000 0x0800_0000 0x1000_0000 0x2000_0000 0x2800_0000 0x3000_0000 0x3800_0000 0x40000_0000 Figure 7 5 NAND Flash Memory Mapping Block Diagram ...

Page 169: ...TION Figure 7 6 A 8 bit NAND Flash Memory Interface Block Diagram NOTE NAND CONTROLLER can support to control two nand flash memories NAND CS Other BOOT nFCE NAND CONTROLLER CS0 Configurable nRCS 1 NAND CONTROLLER CS1 Configurable If you want NAND BOOT by IROM nFCE must be used to boot ...

Page 170: ... 0x2C R 0xXXXX_XXXX NFECCERR0 ECC error status0 register Base 0x30 R 0x0000_0000 NFECCERR1 ECC error status1 register Base 0x34 R 0xXXXX_XXXX NFMECC0 Generated ECC status0 register Base 0x38 R 0xXXXX_XXXX NFMECC1 Generated ECC status1 register Base 0x3C R 0xXXXX_XXXX NFSECC Generated Spare area ECC status register Base 0x40 R 0x0000_0000 NFMLCBITPT 4 bit ECC error bit pattern register Base 0x44 R ...

Page 171: ...000000 TACLS 14 12 CLE ALE duration setting value 0 7 Duration HCLK x TACLS 001 Reserved 11 Reserved 0 TWRPH0 10 8 TWRPH0 duration setting value 0 7 Duration HCLK x TWRPH0 1 000 Reserved 7 Reserved 0 TWRPH1 6 4 TWRPH1 duration setting value 0 7 Duration HCLK x TWRPH1 1 000 PageSize 3 This bit indicates the page size of NAND Flash Memory When PageSize_Ext is 1 the value of PageSize means following ...

Page 172: ...K 0 4 address cycle 1 5 address cycle This bit is determined by OM 1 pin on reset and wake up time from sleep mode This bit can be changed by software later H W Set CfgAddrCycle BusWidth 0 This bit indicates the I O bus width of NAND Flash Memory The value of BusWidth means the followings 0 8 bit bus This bit has no meaning in NAND boot by IROM when the I O bus width is only 8 bit BusWidth has eff...

Page 173: ...ea write or erase command will be invalid and only read command is valid When you try to write or erase locked area the illegal access will be occurred NFSTAT 5 bit will be set If the NFSBLK and NFEBLK are same entire area will be locked 0 Soft Lock 16 Soft Lock configuration 0 Disable lock 1 Enable lock Soft lock area can be modified at any time by software When it is set to 1 the area setting in...

Page 174: ...00034 38 1 SpareECCLock 6 Lock Spare area ECC generation 0 Unlock Spare ECC 1 Lock Spare ECC Spare area ECC status register is NFSECC 0x4E00003C 1 InitMECC 5 1 Initialize main area ECC decoder encoder write only 0 InitSECC 4 1 Initialize spare area ECC decoder encoder write only 0 Reserved 3 Reserved 0 Reg_nCE1 2 NAND Flash Memory nRCS 1 signal control 0 Force nRCS 1 to low Enable chip select 1 Fo...

Page 175: ...ADDRESS REGISTER Register Address R W Description Reset Value NFADDR 0x4E00000C R W NAND Flash address set register 0x0000XX00 REG_ADDR Bit Description Initial State Reserved 31 8 Reserved 0x00 NFADDR 7 0 NAND Flash memory address value 0x00 13 6 DATA REGISTER Register Address R W Description Reset Value NFDATA 0x4E000010 R W NAND Flash data register 0xXXXX NFDATA Bit Description Initial State NFD...

Page 176: ...x00 Reserved 15 8 Not used 0x00 ECCData0 7 0 ECC0 for I O 7 0 0x00 NOTE Only word access is valid NFMECCD1 Bit Description Initial State Reserved 31 24 Not used 0x00 ECCData3 23 16 ECC3 for I O 7 0 0x00 Reserved 15 8 Not used 0x00 ECCData2 7 0 ECC2 for I O 7 0 0x00 13 8 SPARE AREA ECC REGISTER Register Address R W Description Reset Value NFSECCD 0x4E00001C R W NAND Flash ECC Error Correction Code ...

Page 177: ...NAND flash will be locked 0x000000 NFSBLK Bit Description Initial State Reserved 31 24 Reserved 0x00 SBLK_ADDR2 23 16 The 3rd block address of the block erase operation 0x00 SBLK_ADDR1 15 8 The 2nd block address of the block erase operation 0x00 SBLK_ADDR0 7 0 The 1st block address of the block erase operation Only bit 7 5 are valid 0x00 NFEBLK Bit Description Initial State Reserved 31 24 Reserved...

Page 178: ...6 is enabled But cannot be changed when Lock tight bit NFCONT 17 is set when Lock tight 1 or SoftLock 1 NAND flash memory Locked area Read only Prorammable Readable Area Locked area Read only NFSBLK Address High Low NFEBLK 1 NFEBLK NFSBLK Locked Area Read only When NFSBLK NFEBLK NFEBLK Figure 7 7 Softlock and Lock tight ...

Page 179: ...bit ECC decoding is completed 0 IllegalAccess 5 Once Soft Lock or Lock tight is enabled The illegal access program erase to the memory makes this bit set 0 Illegal access is not detected 1 Illegal access is detected 0 RnB_TransDetect 4 When RnB low to high transition is occurred this value set and issue interrupt if enabled To clear this write 1 0 RnB transition is not detected 1 RnB transition is...

Page 180: ...0011 SErrorBitNo 20 18 In spare area Indicates which bit is error 111 MErrorDataNo 17 7 In main data area Indicates which number data is error 0x7FF MErrorBitNo 6 4 In main data area Indicates which bit is error 111 SpareError 3 2 Indicates whether spare area bit fail error occurred 00 No Error 01 1 bit error correctable 10 Uncorrectable 11 ECC area error 10 MainError 1 0 Indicates whether main da...

Page 181: ...eserved Note If it happens that there are more errors than 4 bits 4 bit ECC module does not ensure right detection 000 2nd Bit Error Location 25 16 Error byte location of 2nd bit error 0x00 Reserved 15 10 Reserved 1st Bit Error Location 9 0 Error byte location of 1st bit error 0x00 NOTE These values are updated when ECCDecDone NFSTAT 6 is set 1 NFECCERR1 Bit Description Initial State Reserved 31 2...

Page 182: ...C when read or write main area data while the MainECCLock NFCONT 7 bit is 0 Unlock 13 12 2 When ECCType is 4 bit ECC NFMECC0 Bit Description Initial State 4th Parity 31 24 4th Check Parity generated from main area 0x00 3rd Parity 23 16 3rd Check Parity generated from main area 0x00 2nd Parity 15 8 2nd Check Parity generated from main area 0x00 1st Parity 7 0 1st Check Parity generated from main ar...

Page 183: ...0 0xXX NOTE The NAND flash controller generate NFSECC when read or write spare area data while the SpareECCLock NFCONT 6 bit is 0 Unlock 13 14 4 BIT ECC ERROR PATTEN REGISTER Register Address R W Description Reset Value NFMLCBITPT 0x4E000040 R NAND Flash 4 bit ECC Error Pattern register for data 7 0 0x00000000 NFMLCBITPT Bit Description Initial State 4th Error bit pattern 31 24 4th Error bit patte...

Page 184: ... error 1001 Uncorrectable 1010 1111 reserved b 0000 MLC8ErrLocation2 24 15 Error byte location of 2nd bit error 0x000 Reserved 14 10 Reserved 0x00 MLC8ErrLocation1 9 0 Error byte location of 1st bit error 0x000 NOTE These values are updated when ECCDecodeDone NFSTAT 6 is set 1 NFECCERR1 Bit Description Initial State MLCErrLocation5 31 22 Error byte location of 5th bit error 0x000 Reserved 21 Reser...

Page 185: ...Bit Description Initial State 8th Parity 31 24 8th Check Parity generated from main area 512 byte 0xXX 7th Parity 23 16 7th Check Parity generated from main area 512 byte 0xXX 6th Parity 15 8 6th Check Parity generated from main area 512 byte 0xXX 5th Parity 7 0 5th Check Parity generated from main area 512 byte 0xXX NFM8ECC2 Bit Description Initial State 12th Parity 31 24 12th Check Parity genera...

Page 186: ...0_0000 NFMLC8BITPT0 Bit Description Initial State 4th Error bit pattern 31 24 4th Error bit pattern 0x00 3rd Error bit pattern 23 16 3rd Error bit pattern 0x00 2nd Error bit pattern 15 8 2nd Error bit pattern 0x00 1st Error bit pattern 7 0 1st Error bit pattern 0x00 NFMLC8BITPT1 Bit Description Initial State 8th Error bit pattern 31 24 8th Error bit pattern 0x00 7th Error bit pattern 23 16 7th Err...

Page 187: ...no restrictions In other words each channel can handle the following four cases 1 both source and destination are in the system bus 2 source is in the system bus while destination is in the peripheral bus 3 source is in the peripheral bus while destination is in the system bus 4 both source and destination are in the peripheral bus The main advantage of DMA is that it can transfer the data without...

Page 188: ... as follows Table 8 1 DMA request sources for each channel Bit Source Bit Source Bit Source Bit Source 0 SPI_0_TX 8 Reserved 16 Reserved 24 UART_2 1 1 SPI_0_RX 9 PWM Timer 17 nXDREQ0 25 UART_3 0 2 SPI_1_TX 10 Reserved 18 nXDREQ1 26 UART_3 1 3 SPI_1_RX 11 Reserved 19 UART_0 0 27 PCMOUT 4 I2S TX 12 PCM0 TX 20 UART_0 1 28 PCMIN 5 I2S RX 13 PCM0 RX 21 UART_1 0 29 MICIN 6 I2S1 TX 14 PCM1 TX 22 UART_1 1...

Page 189: ...ed only once in a single service mode The main FSM this FSM counts down the CURR_TC when the sub FSM finishes each of atomic operation In addition this main FSM asserts the INT REQ signal when CURR_TC becomes 0 and the interrupt setting of DCON 29 register is set to 1 In addition it clears DMA ACK if one of the following conditions is met 1 CURR_TC becomes 0 in the whole service mode 2 atomic oper...

Page 190: ... DMA operation The Figure 8 1 shows the basic Timing in the DMA operation of the S3C2416 The setup time and the delay time of XnXDREQ and XnXDACK are same in all the modes If the completion of XnXDREQ meets its setup time it is synchronized twice and then XnXDACK is asserted After assertion of XnXDACK DMA requests the bus and if it gets the bus it performs its operations XnXDACK is deasserted when...

Page 191: ...XnXDREQ 3 1 2 Demand mode If XnXDREQ remains asserted the next transfer starts immediately Otherwise it waits for XnXDREQ to be asserted 3 1 3 Handshake mode If XnXDREQ is deasserted DMA deasserts XnXDACK in 2cycles Otherwise it waits until XnXDREQ is deasserted Caution XnXDREQ has to be asserted low only after the deassertion high of XnXDACK Demand Mode XSCLK XnXDACK XnXDACK XnXDREQ XnXDREQ 2cycl...

Page 192: ...ansfer of these chunk of data thus other bus masters can not get the bus 3 1 5 Burst 4 Transfer Size 4 sequential Reads and 4 sequential Writes are performed in the Burst 4 Transfer NOTE Single Transfer size One read and one write are performed XSCLK XnXDREQ XnXDACK Read Read Read Write Write Write Read Write 3 cycles Double synch Figure 8 3 Burst 4 Transfer size ...

Page 193: ...e is performed XnXDREQ XnXDACK XSCLK XnXDREQ XnXDACK Double synch Read Write Read Write Figure 8 4 Single service Demand Mode Single Transfer Size Single service Handshake Mode Single Transfer Size XnXDREQ XnXDACK XSCLK Read Write Read Write 2cycles Double synch Figure 8 5 Single service Handshake Mode Single Transfer Size Whole service Handshake Mode Single Transfer Size XSCLK XnXDREQ XnXDACK Rea...

Page 194: ...iption Reset Value DISRC0 0x4B000000 R W DMA0 Initial Source Register 0x00000000 DISRC1 0x4B000100 R W DMA1 Initial Source Register 0x00000000 DISRC2 0x4B000200 R W DMA2 Initial Source Register 0x00000000 DISRC3 0x4B000300 R W DMA3 Initial Source Register 0x00000000 DISRC4 0x4B000400 R W DMA4 Initial Source Register 0x00000000 DISRC5 0x4B000500 R W DMA5 Initial Source Register 0x00000000 DISRCn Bi...

Page 195: ...nitial Source Control Register 0x00000000 DISRCC5 0x4B000504 R W DMA5 Initial Source Control Register 0x00000000 DISRCn Bit Description Initial State LOC 1 Bit 1 is used to select the location of source 0 The source is in the system bus AHB 1 The source is in the peripheral bus APB 0 INC 0 Bit 0 is used to select the address increment 0 Increment 1 Fixed If it is 0 the address is increased by its ...

Page 196: ...B000208 R W DMA2 Initial Destination Register 0x00000000 DIDST3 0x4B000308 R W DMA3 Initial Destination Register 0x00000000 DIDST4 0x4B000408 R W DMA4 Initial Destination Register 0x00000000 DIDST5 0x4B000508 R W DMA5 Initial Destination Register 0x00000000 DIDSTn Bit Description Initial State D_ADDR 30 0 These bits are the base address start address of destination for the transfer This value will...

Page 197: ...Destination Control Register 0x00000000 DIDSTn Bit Description Initial State CHK_INT 2 Select interrupt occurrence time when auto reload is setting 0 Interrupt will occur when TC reaches 0 1 Interrupt will occur after auto reload is performed 0 LOC 1 Bit 1 is used to select the location of destination 0 The destination is in the system bus AHB 1 The destination is in the peripheral bus APB 0 INC 0...

Page 198: ... It just de asserts DACK and then starts another transfer if DREQ is asserted We recommend using handshake mode for external DMA request sources to prevent unintended starts of new transfers 0 SYNC 30 Select DREQ DACK synchronization 0 DREQ and DACK are synchronized to PCLK APB clock 1 DREQ and DACK are synchronized to HCLK AHB clock Therefore devices attached to AHB system bus this bit has to be ...

Page 199: ...n set this bit to 1 0 Reserved 23 Reserved for future use 0 RELOAD 22 Set the reload on off option 0 Auto reload is performed when a current value of transfer count becomes 0 i e all the required transfers are performed 1 DMA channel DMA REQ is turned off when a current value of transfer count becomes 0 The channel on off bit DMASKTRIGn 1 is set to 0 DREQ off to prevent unintended further start of...

Page 200: ...ster 000000h DSTAT4 0x4B000414 R DMA4 Count Register 000000h DSTAT5 0x4B000514 R DMA5 Count Register 000000h DSTATn Bit Description Initial State STAT 21 20 Status of this DMA controller 00 It indicates that DMA controller is ready for another DMA request 01 It indicates that DMA controller is busy for transfers 00b CURR_TC 19 0 Current value of transfer count Note that transfer count is initially...

Page 201: ...er 0x00000000 DCSRCn Bit Description Initial State CURR_SRC 30 0 Current source address for DMAn 0x00000000 4 8 CURRENT DESTINATION REGISTER DCDST Register Address R W Description Reset Value DCDST0 0x4B00001C R DMA0 Current Destination Register 0x00000000 DCDST1 0x4B00011C R DMA1 Current Destination Register 0x00000000 DCDST2 0x4B00021C R DMA2 Current Destination Register 0x00000000 DCDST3 0x4B00...

Page 202: ... is turned off DMA request to this channel is ignored 1 DMA channel is turned on and the DMA request is handled This bit is automatically set to off if we set the DCONn 22 bit to no auto reload and or STOP bit of DMASKTRIGn to stop Note that when DCON 22 bit is no auto reload this bit becomes 0 when CURR_TC reaches 0 If the STOP bit is 1 this bit becomes 0 as soon as the current atomic transfer fi...

Page 203: ...gister 000 DMAREQSEL5 0x4B000524 R W DMA5 Request Selection Register 000 DMAREQSELn Bit Description Initial State HWSRCSEL 5 1 Select DMA request source for each DMA Refer to the Table 11 1 on page 11 2 This bits control the 8 1 MUX to select the DMA request source of each DMA These bits have meanings if and only if H W request mode is selected by DMAREQSELn 0 00000 SWHW_SEL 0 Select the DMA sourc...

Page 204: ...DMA CONTROLLER S3C2416X RISC MICROPROCESSOR 8 18 NOTES ...

Page 205: ...n receiving multiple interrupt requests from internal peripherals and external interrupt request pins the interrupt controller requests FIQ or IRQ interrupt of the ARM926EJ core after the arbitration procedure The arbitration procedure depends on the hardware priority logic and the result is written to the interrupt pending register which helps users notify which interrupt is generated out of vari...

Page 206: ...rupt sources and first group has always higher priority than the other group Actually we made this interrupt controller using by two interrupt controllers The nRIQ of ARM926EJ is connected with AND of nIRQs of each interrupt controller The nFIQ is just same Figure 9 2 Interrupt Group Multiplexing Diagram ...

Page 207: ...nterrupt request is pending When the interrupt sources request interrupt service the corresponding bits of SRCPND register are set to 1 and at the same time only one bit of the INTPND register is set to 1 automatically after arbitration procedure If interrupts are masked the corresponding bits of the SRCPND register are set to 1 This does not cause the bit of INTPND register changed When a pending...

Page 208: ...10 NONE Reserved ARB10 NONE Reserved ARB9 NONE Reserved ARB9 NONE Reserved ARB9 NONE Reserved ARB9 NONE Reserved ARB9 NONE Reserved ARB9 NONE Reserved ARB8 NONE Reserved ARB8 NONE Reserved ARB8 NONE Reserved ARB8 NONE Reserved ARB8 NONE Reserved ARB8 NONE Reserved ARB7 NONE Reserved ARB7 NONE Reserved ARB7 INT_I2S0 I2S0 interrupt ARB7 NONE Reserved ARB7 INT_PCM0 PCM0 interrupt ARB7 NONE Reserved A...

Page 209: ...3 Interrupt ERR RXD and TXD ARB3 INT_DMA DMA channel 8 interrupt DMA0 DMA7 ARB3 INT_LCD LCD interrupt LCD Frame FIFO i80 interrupts ARB3 INT_UART2 UART2 Interrupt ERR RXD and TXD ARB2 INT_TIMER4 Timer4 interrupt ARB2 INT_TIMER3 Timer3 interrupt ARB2 INT_TIMER2 Timer2 interrupt ARB2 INT_TIMER1 Timer1 interrupt ARB2 INT_TIMER0 Timer0 interrupt ARB2 INT_WDT_AC97 Watch Dog AC97 interrupt ARB1 INT_TICK...

Page 210: ... 6 1 3 INTERRUPT PRIORITY GENERATING BLOCK The priority logic for 32 interrupt requests is composed of seven rotation based arbiters six first level arbiters and one second level arbiter as shown in Figure 10 2 below Figure 9 3 Priority Generating Block ...

Page 211: ...0 REQ4 REQ1 REQ2 REQ3 and REQ5 Note that REQ0 of an arbiter always has the highest priority and REQ5 has the lowest one In addition by changing the ARB_SEL bits we can rotate the priority of REQ1 to REQ4 Here if ARB_MODE bit is set to 0 ARB_SEL bits are not automatically changed making the arbiter to operate in the fixed priority mode note that even in this mode we can reconfigure the priority by ...

Page 212: ... mode 1 FIQ mode 0x00000000 INTMSK1 0X4A000008 R W Determine which interrupt source of group 1is masked The masked interrupt source will not be serviced 0 Interrupt service is available 1 Interrupt service is masked 0xFFFFFFFF 0X4A00000C INTPND1 0X4A000010 R W Indicate the interrupt request status for group 1 0 The interrupt has not been requested 1 The interrupt source has asserted the interrupt ...

Page 213: ...ce will not be serviced 0 Interrupt service is available 1 Interrupt service is masked 0xFFFFFFFF INTPND2 0X4A000050 R W Indicate the interrupt request status for group 2 0 The interrupt has not been requested 1 The interrupt source has asserted the interrupt request 0x00000000 INTOFFSET2 0X4A000054 R Indicate the IRQ interrupt request source for group 2 0x00000000 PRIORITY_MODE2 0x4A000070 R W IR...

Page 214: ...e another valid request from the same source you should clear the corresponding bit first and then enable the interrupt You can clear a specific bit of the SRCPND register by writing a data to this register It clears only the bit positions of the SRCPND corresponding to those set to one in the data The bit positions corresponding to those that are set to 0 in the data remains as they are SOURCE PE...

Page 215: ...d 0 INT_TICK 8 0 Not requested 1 Requested 0 nBATT_FLT 7 0 Not requested 1 Requested 0 Reserved 6 0 Not requested 1 Requested 0 EINT8_15 5 0 Not requested 1 Requested 0 EINT4_7 4 0 Not requested 1 Requested 0 EINT3 3 0 Not requested 1 Requested 0 EINT2 2 0 Not requested 1 Requested 0 EINT1 1 0 Not requested 1 Requested 0 EINT0 0 0 Not requested 1 Requested 0 SRCPND 2 Bit Description Initial State ...

Page 216: ...Interrupt mode regiseter for group 2 0 IRQ mode 1 FIQ mode 0x00000000 NOTE If an interrupt mode is set to FIQ mode in the INTMOD register FIQ interrupt will not affect both INTPND and INTOFFSET registers In this case the two registers are valid only for IRQ mode interrupt source INTMOD1 Bit Description Initial State INT_ADC 31 0 IRQ 1 FIQ 0 INT_RTC 30 0 IRQ 1 FIQ 0 Reserved 29 0 IRQ 1 FIQ 0 INT_UA...

Page 217: ...0 IRQ 1 FIQ 0 EINT8_15 5 0 IRQ 1 FIQ 0 EINT4_7 4 0 IRQ 1 FIQ 0 EINT3 3 0 IRQ 1 FIQ 0 EINT2 2 0 IRQ 1 FIQ 0 EINT1 1 0 IRQ 1 FIQ 0 EINT0 0 0 IRQ 1 FIQ 0 INTMOD2 Bit Description Initial State Reserved 7 0 IRQ 1 FIQ 0 INT_I2S0 6 0 IRQ 1 FIQ 0 Reserved 5 0 IRQ 1 FIQ 0 INT_PCM0 4 0 IRQ 1 FIQ 0 Reserved 3 0 IRQ 1 FIQ 0 Reserved 2 0 IRQ 1 FIQ 0 Reserved 1 0 IRQ 1 FIQ 0 INT_2D 0 0 IRQ 1 FIQ 0 ...

Page 218: ...masked 0xFFFFFFFF INTMSK1 Bit Description Initial State INT_ADC 31 0 Service available 1 Masked 1 INT_RTC 30 0 Service available 1 Masked 1 Reserved 29 0 Service available 1 Masked 1 INT_UART0 28 0 Service available 1 Masked 1 INT_IIC0 27 0 Service available 1 Masked 1 INT_USBH 26 0 Service available 1 Masked 1 INT_USBD 25 0 Service available 1 Masked 1 INT_NAND 24 0 Service available 1 Masked 1 I...

Page 219: ...ervice available 1 Masked 1 EINT2 2 0 Service available 1 Masked 1 EINT1 1 0 Service available 1 Masked 1 EINT0 0 0 Service available 1 Masked 1 INTMSK2 Bit Description Initial State Reserved 7 0 Service available 1 Masked 1 INT_I2S0 6 0 Service available 1 Masked 1 Reserved 5 0 Service available 1 Masked 1 INT_PCM0 4 0 Service available 1 Masked 1 Reserved 3 0 Service available 1 Masked 1 Reserve...

Page 220: ...est 0x00000000 INTPND2 0X4A000050 R W Indicate the interrupt request status for group 2 0 The interrupt has not been requested 1 The interrupt source has asserted the interrupt request 0x00000000 NOTES 1 If the FIQ mode interrupt occurs the corresponding bit of INTPND will not be turned on as the INTPND register is available only for IRQ mode interrupt 2 Cautions in clearing the INTPND register Th...

Page 221: ...d 0 INT_TICK 8 0 Not requested 1 Requested 0 nBATT_FLT 7 0 Not requested 1 Requested 0 Reserved 6 0 Not requested 1 Requested 0 EINT8_15 5 0 Not requested 1 Requested 0 EINT4_7 4 0 Not requested 1 Requested 0 EINT3 3 0 Not requested 1 Requested 0 EINT2 2 0 Not requested 1 Requested 0 EINT1 1 0 Not requested 1 Requested 0 EINT0 0 0 Not requested 1 Requested 0 INTPND2 Bit Description Initial State I...

Page 222: ...p 1 The OFFSET Value INT_ADC 31 INT_UART2 15 INT_RTC 30 INT_TIMER4 14 Reserved 29 INT_TIMER3 13 INT_UART0 28 INT_TIMER2 12 INT_IIC0 27 INT_TIMER1 11 INT_USBH 26 INT_TIMER0 10 INT_USBD 25 INT_WDT AC97 9 INT_NAND 24 INT_TICK 8 INT_UART1 23 nBATT_FLT 7 INT_SPI0 22 Reserved 6 INT_SDI0 21 EINT8_15 5 INT_SDI1 20 EINT4_7 4 Reserved 19 EINT3 3 INT_UART3 18 EINT2 2 INT_DMA 17 EINT1 1 INT_LCD 16 EINT0 0 INT...

Page 223: ...roup 2 The OFFSET Value INT Source for group 2 The OFFSET Value Reserved 19 Reserved 3 Reserved 18 Reserved 2 Reserved 17 Reserved 1 Reserved 16 INT_2D 0 NOTE FIQ mode interrupt does not affect the INTOFFSET register as the register is available only for IRQ mode interrupt ...

Page 224: ..._WDT 27 0 Not requested 1 Requested INT_WDT_AC97 0 SUBINT_ERR3 26 0 Not requested 1 Requested 0 SUBINT_TXD3 25 0 Not requested 1 Requested 0 SUBINT_RXD3 24 0 Not requested 1 Requested INT_UART3 0 SUBINT_DMA5 23 0 Not requested 1 Requested 0 SUBINT_DMA4 22 0 Not requested 1 Requested 0 SUBINT_DMA3 21 0 Not requested 1 Requested 0 SUBINT_DMA2 20 0 Not requested 1 Requested 0 SUBINT_DMA1 19 0 Not req...

Page 225: ...tial State SUBINT_ERR1 5 0 Not requested 1 Requested 0 SUBINT_TXD1 4 0 Not requested 1 Requested 0 SUBINT_RXD1 3 0 Not requested 1 Requested INT_UART1 0 SUBINT_ERR0 2 0 Not requested 1 Requested 0 SUBINT_TXD0 1 0 Not requested 1 Requested 0 SUBINT_RXD0 0 0 Not requested 1 Requested INT_UART0 0 ...

Page 226: ...SUBINT_AC97 28 0 Service available 1 Masked 1 SUBINT_WDT 27 0 Service available 1 Masked INT_WDT_AC97 1 SUBINT_ERR3 26 0 Service available 1 Masked 1 SUBINT_TXD3 25 0 Service available 1 Masked 1 SUBINT_RXD3 24 0 Service available 1 Masked INT_UART3 1 SUBINT_DMA5 23 0 Service available 1 Masked 1 SUBINT_DMA4 22 0 Service available 1 Masked 1 SUBINT_DMA3 21 0 Service available 1 Masked 1 SUBINT_DMA...

Page 227: ...0 Service available 1 Masked 1 SUBINT_ERR1 5 0 Service available 1 Masked 1 SUBINT_TXD1 4 0 Service available 1 Masked 1 SUBINT_RXD1 3 0 Service available 1 Masked INT_UART1 1 SUBINT_ERR0 2 0 Service available 1 Masked 1 SUBINT_TXD0 1 0 Service available 1 Masked 1 SUBINT_RXD0 0 0 Service available 1 Masked INT_UART0 1 ...

Page 228: ...4 1 2 3 5 2 ARB_MODE6 1 b1 000 REQ 0 1 2 3 4 5 001 REQ 1 2 3 4 5 0 010 REQ 2 3 4 5 0 1 011 REQ 3 4 5 0 1 2 100 REQ 4 5 0 1 2 3 101 REQ 5 0 1 2 3 4 0 ARB_MODE5 23 Arbiter 5 group priority mode selection 0 Fixed ends Rotate middle 0 ARB_SEL5 22 20 Arbiter 5 group priority order set 1 ARB_MODE5 1 b0 00 REQ 0 1 2 3 4 5 01 REQ 0 2 3 4 1 5 10 REQ 0 3 4 1 2 5 11 REQ 0 4 1 2 3 5 0 ARB_MODE4 19 Arbiter 4 g...

Page 229: ...oup priority mode selection 0 Fixed ends Rotate middle 1 Rotate all 0 ARB_SEL2 10 8 Arbiter 2 group priority order set 1 ARB_MODE2 1 b0 00 REQ 0 1 2 3 4 5 01 REQ 0 2 3 4 1 5 10 REQ 0 3 4 1 2 5 11 REQ 0 4 1 2 3 5 2 ARB_MODE2 1 b1 000 REQ 0 1 2 3 4 5 001 REQ 1 2 3 4 5 0 010 REQ 2 3 4 5 0 1 011 REQ 3 4 5 0 1 2 100 REQ 4 5 0 1 2 3 101 REQ 5 0 1 2 3 4 0 ARB_MODE1 7 Arbiter 1 group priority mode selecti...

Page 230: ...Bit Description Initial State 101 REQ 5 0 1 2 3 4 ARB_MODE0 3 Arbiter 0 group priority mode selection 0 Fixed ends Rotate middle 0 ARB_SEL0 2 0 Arbiter 0 group priority order set 1 ARB_MODE0 1 b0 00 REQ 0 1 2 3 4 5 01 REQ 0 2 3 4 1 5 10 REQ 0 3 4 1 2 5 11 REQ 0 4 1 2 3 5 0 ...

Page 231: ...mode selection 0 Fixed ends Rotate middle 0 ARB_SEL12 22 20 Arbiter 12 group priority order set 1 ARB_MODE12 1 b0 00 REQ 0 1 2 3 4 5 01 REQ 0 2 3 4 1 5 10 REQ 0 3 4 1 2 5 11 REQ 0 4 1 2 3 5 0 ARB_MODE11 19 Arbiter 11 group priority mode selection 0 Fixed ends Rotate middle 1 Rotate all 0 ARB_SEL11 18 16 Arbiter 11 group priority order set 1 ARB_MODE11 1 b0 00 REQ 0 1 2 3 4 5 01 REQ 0 2 3 4 1 5 10 ...

Page 232: ...B_MODE9 1 b0 00 REQ 0 1 2 3 4 5 01 REQ 0 2 3 4 1 5 10 REQ 0 3 4 1 2 5 11 REQ 0 4 1 2 3 5 2 ARB_MODE9 1 b1 000 REQ 0 1 2 3 4 5 001 REQ 1 2 3 4 5 0 010 REQ 2 3 4 5 0 1 011 REQ 3 4 5 0 1 2 100 REQ 4 5 0 1 2 3 101 REQ 5 0 1 2 3 4 0 ARB_MODE8 7 Arbiter 8 group priority mode selection 0 Fixed ends Rotate middle 1 Rotate all 0 ARB_SEL8 6 4 Arbiter 8 group priority order set 1 ARB_MODE8 1 b0 00 REQ 0 1 2 ...

Page 233: ...biter 6 group priority rotate enable 0 Priority does not rotate 1 Priority rotate enable 1 ARB_UPDATE5 5 Arbiter 5 group priority rotate enable 0 Priority does not rotate 1 Priority rotate enable 1 ARB_UPDATE4 4 Arbiter 4 group priority rotate enable 0 Priority does not rotate 1 Priority rotate enable 1 ARB_UPDATE3 3 Arbiter 3 group priority rotate enable 0 Priority does not rotate 1 Priority rota...

Page 234: ...TE11 4 Arbiter 11 group priority rotate enable 0 Priority does not rotate 1 Priority rotate enable 1 ARB_UPDATE10 3 Arbiter 10 group priority rotate enable 0 Priority does not rotate 1 Priority rotate enable 1 ARB_UPDATE9 2 Arbiter 9 group priority rotate enable 0 Priority does not rotate 1 Priority rotate enable 1 ARB_UPDATE8 1 Arbiter 8 group priority rotate enable 0 Priority does not rotate 1 P...

Page 235: ...E GPE 16 input output port Port F GPF 8 input output port Port G GPG 8 input output port Port H GPH 15 input output port Port K GPK 16 input output port Port L GPL 7 input output port Port M GPM 2 input port Each port can be easily configured by software to meet various system configurations and design requirements You have to define which function of each pin is used before starting the main prog...

Page 236: ...tput only nFRE GPA19 Output only nFWE GPA18 Output only ALE GPA17 Output only CLE GPA16 Output only nRCS5 GPA15 Output only nRCS4 GPA14 Output only nRCS3 GPA13 Output only nRCS2 GPA12 Output only nRCS1 Reserved Output only Reserved GPA10 Reserved RADDR25 GPA9 Output only RADDR24 GPA8 Output only RADDR23 GPA7 Output only RADDR22 GPA6 Output only RADDR21 GPA5 Output only RADDR20 GPA4 Output only RAD...

Page 237: ...put TOUT3 GPB2 Input output TOUT2 GPB1 Input output TOUT1 GPB0 Input output TOUT0 Port C Selectable Pin Functions GPC15 Input output RGB_VD7 SYS_VD7 GPC14 Input output RGB_VD6 SYS_VD6 GPC13 Input output RGB_VD5 SYS_VD5 GPC12 Input output RGB_VD4 SYS_VD4 GPC11 Input output RGB_VD3 SYS_VD3 GPC10 Input output RGB_VD2 SYS_VD2 GPC9 Input output RGB_VD1 SYS_VD1 GPC8 Input output RGB_VD0 SYS_VD0 GPC7 Inp...

Page 238: ...GB_VD12 SYS_VD12 GPD3 Input output RGB_VD11 SYS_VD11 GPD2 Input output RGB_VD10 SYS_VD10 GPD1 Input output RGB_VD9 SYS_VD9 GPD0 Input output RGB_VD8 SYS_VD8 Port E Selectable Pin Functions GPE15 Input output IICSDA GPE14 Input output IICSCL GPE13 Input output SPICLK0 GPE12 Input output SPIMOSI0 GPE11 Input output SPIMISO0 GPE10 Input output SD0_DAT3 GPE9 Input output SD0_DAT2 GPE8 Input output SD0...

Page 239: ...table Pin Functions Reserved Input output Reserved Reserved Reserved Input output Reserved Reserved Reserved Input output Reserved Reserved Reserved Input output Reserved Reserved Reserved Input output Reserved Reserved Reserved Input output Reserved Reserved Reserved Input output Reserved Reserved Reserved Input output Reserved Reserved GPG7 Input output EINT15 GPG6 Input output EINT14 GPG5 Input...

Page 240: ...t output RXD2 GPH4 Input output TXD2 GPH3 Input output RXD1 GPH2 Input output TXD1 GPH1 Input output RXD0 GPH0 Input output TXD0 Port K Selectable Pin Functions GPK15 Input output SDATA31 GPK14 Input output SDATA30 GPK13 Input output SDATA29 GPK12 Input output SDATA28 GPK11 Input output SDATA27 GPK10 Input output SDATA26 GPK9 Input output SDATA25 GPK8 Input output SDATA24 GPK7 Input output SDATA23...

Page 241: ...erved Input output Reserved GPL9 Input output SD1_CLK GPL8 Input output SD1_CMD Reserved Input output Reserved Reserved Reserved Reserved Input output Reserved Reserved Reserved Reserved Input output Reserved Reserved Reserved Reserved Input output Reserved Reserved Reserved GPL3 Input output SD1_DAT3 GPL2 Input output SD1_DAT2 GPL1 Input output SD1_DAT1 GPL0 Input output SD1_DAT0 Port M Selectabl...

Page 242: ...ull down resister is disabled If the port pull down register is enabled then the pull down resisters work without pin s functional setting input output DATAn EINTn and etc 2 4 MISCELLANEOUS CONTROL REGISTER This register controls mode selection and CLKOUT selection 2 5 EXTERNAL INTERRUPT CONTROL REGISTER The 16 external interrupts are requested by various signaling methods The EXTINT register conf...

Page 243: ...24 0 Output 1 RSMAVD GPA23 23 0 Output 1 RSMCLK GPA22 22 0 Output 1 nFCE GPA21 21 0 Output 1 nRSTOUT GPA20 20 0 Output 1 nFRE GPA19 19 0 Output 1 nFWE GPA18 18 0 Output 1 ALE GPA17 17 0 Output 1 CLE GPA16 16 0 Output 1 nRCS 5 GPA15 15 0 Output 1 nRCS 4 GPA14 14 0 Output 1 nRCS 3 GPA13 13 0 Output 1 nRCS 2 GPA12 12 0 Output 1 nRCS 1 Reserved 11 Reserved GPA10 10 0 Reserved 1 RADDR25 GPA9 9 0 Output...

Page 244: ...ription Reserved 31 27 Reserved GPA 27 0 26 0 When the port is configured as output port the pin state is the same as the corresponding bit When the port is configured as functional pin the undefined value will be read NOTE GPA10 is excluded in data output mode ...

Page 245: ...DACK 0 11 XDACK 0 Reserved 17 16 Reserved Reserved 15 14 Reserved GPB6 13 12 00 Input 01 Output 10 nXBREQ 11 XBREQ GPB5 11 10 00 Input 01 Output 10 nXBACK 11 XBACK GPB4 9 8 00 Input 01 Output 10 TCLK 11 reserved GPB3 7 6 00 Input 01 Output 10 TOUT3 11 reserved GPB2 5 4 00 Input 01 Output 10 TOUT2 11 reserved GPB1 3 2 00 Input 01 Output 10 TOUT1 11 reserved GPB0 1 0 00 Input 01 Output 10 TOUT0 11 r...

Page 246: ...erved GPBUDP10 GPBUDP0 21 20 1 0 CPU CPD 00 pull up down disable 01 pull down enable 10 pull up enable 11 not available GPBSEL Bit Description Reserved 31 5 Reserved GPB10SEL 4 0 GPB10 1 I2SSDO_2 GPB9SEL 3 0 GPB9 1 I2SSDO_1 Reserved 2 Reserved Reserved 1 Reserved GPB6SEL 0 0 GPB6 1 RTCK ...

Page 247: ... 24 00 Input 01 Output 10 RGB SYS_VD 4 11 Reserved GPC11 23 22 00 Input 01 Output 10 RGB SYS_VD 3 11 Reserved GPC10 21 20 00 Input 01 Output 10 RGB SYS_VD 2 11 Reserved GPC9 19 18 00 Input 01 Output 10 RGB SYS_VD 1 11 Reserved GPC8 17 16 00 Input 01 Output 10 RGB SYS_VD 0 11 Reserved GPC7 15 14 00 Input 01 Output 10 Reserved 11 Reserved GPC6 13 12 00 Input 01 Output 10 Reserved 11 Reserved GPC5 11...

Page 248: ... the corresponding bit is the pin state When the port is configured as output port the pin state is the same as the corresponding bit When the port is configured as functional pin the undefined value will be read GPCUDP Bit Description GPCUDP15 PCUDP0 31 30 1 0 CPU CPD 00 pull up down disable 01 pull down enable 10 pull up enable 11 not available ...

Page 249: ...24 00 Input 01 Output 10 RGB_VD 20 11 Reserved GPD11 23 22 00 Input 01 Output 10 RGB_VD 19 11 Reserved GPD10 21 20 00 Input 01 Output 10 RGB_VD 18 11 Reserved GPD9 19 18 00 Input 01 Output 10 RGB SYS_VD 17 11 Reserved GPD8 17 16 00 Input 01 Output 10 RGB SYS _VD 16 11 Reserved GPD7 15 14 00 Input 01 Output 10 RGB SYS _VD 15 11 Reserved GPD6 13 12 00 Input 01 Output 10 RGB SYS _VD 14 11 Reserved GP...

Page 250: ...the corresponding bit is the pin state When the port is configured as output port the pin state is the same as the corresponding bit When the port is configured as functional pin the undefined value will be read GPDUDP Bit Description GPDUDP15 GPDUDP0 31 30 1 0 CPU CPD 00 pull up down disable 01 pull down enable 10 pull up enable 11 not available ...

Page 251: ...7 26 00 Input 01 Output 10 SPICLK0 11 Reserved GPE12 25 24 00 Input 01 Output 10 SPIMOSI0 11 Reserved GPE11 23 22 00 Input 01 Output 10 SPIMISO0 11 Reserved GPE10 21 20 00 Input 01 Output 10 SD0_DAT3 11 Reserved GPE9 19 18 00 Input 01 Output 10 SD0_DAT2 11 Reserved GPE8 17 16 00 Input 01 Output 10 SD0_DAT1 11 Reserved GPE7 15 14 00 Input 01 Output 10 SD0_DAT0 11 Reserved GPE6 13 12 00 Input 01 Out...

Page 252: ...tate is the same as the corresponding bit When the port is configured as a functional pin the undefined value will be read GPEUDP Bit Description GPEUDP15 GPEUDP0 31 30 1 0 CPU CPD 00 pull up down disable 01 pull down enable 10 pull up enable 11 not available GPESEL Bit Description Reserved 31 5 Reserved GPE4SEL 4 0 GPE4 1 PCM_SDO GPE3SEL 3 0 GPE3 1 PCM_SDI GPE2SEL 2 0 GPE2 1 PCM_CDCLK GPE1SEL 1 0...

Page 253: ... Reserved GPF5 11 10 00 Input 01 Output 10 EINT 5 11 Reserved GPF4 9 8 00 Input 01 Output 10 EINT 4 11 Reserved GPF3 7 6 00 Input 01 Output 10 EINT 3 11 Reserved GPF2 5 4 00 Input 01 Output 10 EINT 2 11 Reserved GPF1 3 2 00 Input 01 Output 10 EINT 1 11 Reserved GPF0 1 0 00 Input 01 Output 10 EINT 0 11 Reserved GPFDAT Bit Description Reserved 31 8 Reserved GPF 7 0 7 0 When the port is configured as...

Page 254: ...55 GPGCON Bit Description Reserved 31 30 Reserved Reserved 29 28 Reserved Reserved 27 26 Reserved Reserved 25 24 Reserved Reserved 23 22 Reserved Reserved 21 20 Reserved Reserved 19 18 Reserved Reserved 17 16 Reserved GPG7 15 14 00 Input 01 Output 10 EINT 15 11 Reserved GPG6 13 12 00 Input 01 Output 10 EINT 14 11 Reserved GPG5 11 10 00 Input 01 Output 10 EINT 13 11 Reserved GPG4 9 8 00 Input 01 Ou...

Page 255: ...he corresponding bit is the pin state When the port is configured as an output port the pin state is the same as the corresponding bit When the port is configured as functional pin the undefined value will be read GPGUDP Bit Description GPGUDP7 GPGUDP0 15 14 1 0 CPU CPD 00 pull up down disable 01 pull down enable 10 pull up enable 11 not available ...

Page 256: ...10 CLKOUT0 11 Reserved GPH12 25 24 00 Input 01 Output 10 EXTUARTCLK 11 Reserved GPH11 23 22 00 Input 01 Output 10 nRTS1 11 Reserved GPH10 21 20 00 Input 01 Output 10 nCTS1 11 Reserved GPH9 19 18 00 Input 01 Output 10 nRTS0 11 Reserved GPH8 17 16 00 Input 01 Output 10 nCTS0 11 Reserved GPH7 15 14 00 Input 01 Output 10 RXD 3 11 nCTS2 GPH6 13 12 00 Input 01 Output 10 TXD 3 11 nRTS2 GPH5 11 10 00 Inpu...

Page 257: ...nding bit is the pin state When the port is configured as an output port the pin state is the same as the corresponding bit When the port is configured as functional pin the undefined value will be read GPHUDP Bit Description Reserved 31 30 Reserved GPHUDP14 GPHUDP0 29 28 1 0 CPU CPD 00 pull up down disable 01 pull down enable 10 pull up enable 11 not available ...

Page 258: ... 11 Reserved GPK12 25 24 00 Input 01 Output 10 Sdata 28 11 Reserved GPK11 23 22 00 Input 01 Output 10 Sdata 27 11 Reserved GPK10 21 20 00 Input 01 Output 10 Sdata 26 11 Reserved GPK9 19 18 00 Input 01 Output 10 Sdata 25 11 Reserved GPK8 17 16 00 Input 01 Output 10 Sdata 24 11 Reserved GPK7 15 14 00 Input 01 Output 10 Sdata 23 11 Reserved GPK6 13 12 00 Input 01 Output 10 Sdata 22 11 Reserved GPK5 1...

Page 259: ...nding bit is the pin state When the port is configured as an output port the pin state is the same as the corresponding bit When the port is configured as functional pin the undefined value will be read GPKUDP Bit Description GPKUDP15 GPKUDP0 31 30 1 0 CPU CPD 00 pull up down disable 01 pull down enable 10 pull up enable 11 not available ...

Page 260: ...PL9 19 18 00 Input 01 Output 10 SD1_CLK 11 Reserved GPL8 17 16 00 Input 01 Output 10 SD1_CMD 11 Reserved Reserved 15 14 Reserved Reserved 13 12 Reserved Reserved 11 10 Reserved Reserved 9 8 Reserved GPL3 7 6 00 Input 01 Output 10 SD1_DAT3 11 Reserved GPL2 5 4 00 Input 01 Output 10 SD1_DAT2 11 Reserved GPL1 3 2 00 Input 01 Output 10 SD1_DAT1 11 Reserved GPL0 1 0 00 Input 01 Output 10 SD1_DAT0 11 Re...

Page 261: ...3C2416 RISC MICROPROCESSOR I O PORTS 10 27 GPLUDP Bit Description Reserved 31 28 Reserved GPLUDP13 GPLUDP0 27 26 1 0 CPU CPD 00 pull up down disable 01 pull down enable 10 pull up enable 11 not available ...

Page 262: ...t 10 FRnB GPM0 1 0 Others GPM Input 10 RSMBWAIT GPMDAT Bit Description Reserved 31 2 Reserved GPM 1 0 1 0 When the port is configured as an input port the corresponding bit is the pin state When the port is configured as functional pin the undefined value will be read GPMUDP Bit Description Reserved 31 6 Reserved nWAIT 5 4 CPU CPD 00 pull up down disable 01 pull down enable 10 pull up enable 11 no...

Page 263: ...1 Must be set 1 1 Reserved 30 Reserved 1 Reserved 29 Reserved 0 Reserved 28 Should be 1 1 Reserved 27 25 Reserved 000 FLT_I2C 24 Clocked Noise Filter Enable for IIC 0 Reserved 23 13 Reserved 0 SEL_SUSPND 12 USB Port Suspend mode 0 Normal mode 1 Suspend mode 0 Reserved 11 Reserved 0 CLKSEL1 10 8 Select source clock with CLKOUT1 pad 000 RESERVED 001 Gated EPLL output 010 RTC clock output 011 HCLK 10...

Page 264: ...ion is DCLK1DIV 1 n 1 DCLK1DIV 23 20 DCLK1 divide value DCLK1 frequency source clock DCLK1DIV 1 DCLK1SelCK 17 Select DCLK1 source clock 0 PCLK 1 EPLL DCLK1EN 16 DCLK1 enable 0 DCLK1 disable 1 DCLK1 enable DCLK0CMP 11 8 DCLK0 compare value clock toggle value DCLK0DIV If the DCLK0CMP is n Low level duration is n 1 High level duration is DCLK0DIV 1 n 1 DCLK0DIV 7 4 DCLK0 divide value DCLK0 frequency ...

Page 265: ...rnal interrupt control register 1 0x0 EXTINT0 Bit Description Reserved 31 Reserved EINT7 30 28 Setting the signalling method of the EINT7 000 Low level 001 High level 01x Falling edge triggered 10x Rising edge triggered 11x Both edge triggered Reserved 27 Reserved EINT6 26 24 Setting the ٛsignalling method of the EINT6 000 Low level 001 High level 01x Falling edge triggered 10x Rising edge trigger...

Page 266: ...ved 3 Reserved EINT0 2 0 Setting the signalling method of the EINT0 000 Low level 001 High level 01x Falling edge triggered 10x Rising edge triggered 11x Both edge triggered EXTINT1 Bit Description Reserved 31 Reserved EINT15 30 28 Setting the signaling method of the EINT15 000 Low level 001 High level 01x Falling edge triggered 10x Rising edge triggered 11x Both edge triggered Reserved 27 Filter ...

Page 267: ...ge triggered 11x Both edge triggered Reserved 11 Reserved EINT10 10 8 Setting the signaling method of the EINT10 000 Low level 001 High level 01x Falling edge triggered 10x Rising edge triggered 11x Both edge triggered Reserved 7 Reserved EINT9 6 4 Setting the signaling method of the EINT9 000 Low level 001 High level 01x Falling edge triggered 10x Rising edge triggered 11x Both edge triggered Res...

Page 268: ...ved 19 Reserved Reserved 18 Reserved Reserved 17 Reserved Reserved 16 Reserved EINT15 15 0 enable interrupt 1 masked EINT14 14 0 enable interrupt 1 masked EINT13 13 0 enable interrupt 1 masked EINT12 12 0 enable interrupt 1 masked EINT11 11 0 enable interrupt 1 masked EINT10 10 0 enable interrupt 1 masked EINT9 9 0 enable interrupt 1 masked EINT8 8 0 enable interrupt 1 masked EINT7 7 0 enable inte...

Page 269: ...y writing 1 0 Not occur 1 Occur interrupt 0 EINT13 13 It is cleared by writing 1 0 Not occur 1 Occur interrupt 0 EINT12 12 It is cleared by writing 1 0 Not occur 1 Occur interrupt 0 EINT11 11 It is cleared by writing 1 0 Not occur 1 Occur interrupt 0 EINT10 10 It is cleared by writing 1 0 Not occur 1 Occur interrupt 0 EINT9 9 It is cleared by writing 1 0 Not occur 1 Occur interrupt 0 EINT8 8 It is...

Page 270: ...R External pin status Not define GSTATUS1 0x560000b0 R Software Platform ID register 0x32416X001 GSTATUS0 Bit Description Reserved 31 4 Reserved nWAIT 3 Status of nWAIT pin NCON 2 Status of NCON pin RnB 1 Status of RnB pin BATT_FLT 0 Status of BATT_FLT pin GSTATUS1 Bit Description Software Platform ID 31 0 Software Platform ID register 0x32416X003 ...

Page 271: ...0 DSC_nROE 25 24 10 DSC_nRWE 23 22 nRBE nROE nRWE Drive strength 00 5 2mA 01 10 5mA 10 15 7mA 11 21 0mA 10 DSC_nRCS5 21 20 10 DSC_nRCS4 19 18 10 DSC_nRCS3 17 16 10 DSC_nRCS2 15 14 10 DSC_nRCS1 13 12 10 DSC_nRCS0 11 10 nRCS5 nRCS0 Address Bus Drive strength 00 5 2mA 01 10 5mA 10 15 7mA 11 21 0mA 10 DSC_RADDRH 9 8 ROM Address Bus 25 16 Drive strength 00 5 2mA 01 10 5mA 10 15 7mA 11 21 0mA 10 DSC_RAD...

Page 272: ...0 4 9mA 01 9 8mA 10 14 8mA 11 19 7mA 10 DSC_nSRAS 15 14 nSRAS drive strength 00 4 9mA 01 9 8mA 10 14 8mA 11 19 7mA 10 DSC_nSCS1 13 12 nSCS1 drive strength 00 4 9mA 01 9 8mA 10 14 8mA 11 19 7mA 10 DSC_nSCS0 11 10 nSCS0 drive strength 00 4 9mA 01 9 8mA 10 14 8mA 11 19 7mA 10 DSC_SADDR 9 8 SADDR drive strength 00 4 9mA 01 9 8mA 10 14 8mA 11 19 7mA 10 DSC_SDATA3 7 6 SDATA 31 24 drive strength 00 4 9mA...

Page 273: ...5mA 10 15 7mA 11 21 0mA 10 Reserved 17 16 Reserved 00 DSC_RSMAVD 15 14 RSMAVD drive strength 00 5 2mA 01 10 5mA 10 15 7mA 11 21 0mA 10 DSC_RSMCLK 13 12 RSMCLK drive strength 00 5 2mA 01 10 5mA 10 15 7mA 11 21 0mA 10 DSC_DQM3 11 10 DQM3 drive strength 00 4 9mA 01 9 8mA 10 14 8mA 11 19 7mA 10 DSC_DQM2 9 8 DQM2 drive strength 00 4 9mA 01 9 8mA 10 14 8mA 11 19 7mA 10 DSC_DQM1 7 6 DQM1 drive strength 0...

Page 274: ... 2 6mA 01 5 2mA 10 7 8mA 11 10 5mA 10 DSC_LCD1 7 6 LCD_VD 15 8 drive strength 00 2 6mA 01 5 2mA 10 7 8mA 11 10 5mA 10 DSC_LCD0 5 4 LCD_VD 7 0 drive strength 00 2 6mA 01 5 2mA 10 7 8mA 11 10 5mA 10 DSC_HS_MMC 3 2 HS_MMC drive strength 00 2 6mA 01 5 2mA 10 7 8mA 11 10 5mA 10 DSC_HS_SPI 1 0 HS_SPI drive strength 00 2 6mA 01 5 2mA 10 7 8mA 11 10 5mA 10 ...

Page 275: ...tput 0 01 output 1 10 Hi Z 11 Not Available 01 PSC_DQS 15 14 DQS 1 0 pin status inactive 0 00 output 0 01 output 1 10 Hi Z 11 Not Available 00 PSC_nSWE 13 12 nSWE pin status inactive 1 00 output 0 01 output 1 10 Hi Z 11 Not Available 01 PSC_SDR 11 10 nSCAS nSRAS pin status inactive 1 00 output 0 01 output 1 10 Hi Z 11 Not Available 01 PSC_nSCS1 9 8 nSCS1 pin status inactive 1 00 output 0 01 output...

Page 276: ...active 1 00 output 0 01 output 1 10 Hi Z 11 Not Available 01 PSC_nROE 17 16 nROE pin status inactive 1 00 output 0 01 output 1 10 Hi Z 11 Not Available 01 PSC_RSM 15 14 RSMCLK GPA23 RSMAVD GPA24 pin status inactive 0 00 output 0 01 output 1 10 Hi Z 11 Not Available 00 PSC_nRBE 13 12 nRBE 1 0 pin status inactive 1 00 output 0 01 output 1 10 Hi Z 11 Not Available 01 PSC_nRCS51 11 10 nRCS 5 1 GPA 16 ...

Page 277: ... 43 PDSMCON Bit Description Reset Value PSC_RADDRL 3 2 RADDR 15 1 pin status inactive 0 00 output 0 01 output 1 10 Hi Z 11 Not Available 00 PSC_RADDR0 1 0 RADDR 0 GPA 0 pin status inactive 0 00 output 0 01 output 1 10 Hi Z 11 Not Available 00 ...

Page 278: ...F 7 0 GPG 7 0 GPA GPB GPC GPD GPE GPG 15 8 GPH GPK GPL GPM SFR GPACON 27 0 GPADAT 27 0 GPFCON 15 0 GPFDAT 7 0 GPFUDP 15 0 GPGCONL 15 0 GPGDATL 7 0 GPGUDPL 15 0 GPKCON 31 0 GPKDAT 15 0 GPKUDP 31 0 EXTINT0 31 0 EXINT1 31 0 PDDMCON PDSMCON All registers except alive SFR GP CON GP DAT GP UDP ...

Page 279: ... The watchdog timer generates the reset signal It can be used as a normal 16 bit interval timer to request interrupt service Advantage in using WDT instead of PWM timer is that WDT generates the reset signal 1 1 FEATURES The Watchdog Timer includes the following features Normal interval timer mode with interrupt request Internal reset signal is activated for 128 PCLK cycles when the timer count va...

Page 280: ...equency division factor can be selected as 16 32 64 or 128 Use the following equation to calculate the watchdog timer clock frequency and the duration of each timer clock cycle t_watchdog 1 PCLK Prescaler value 1 Division_factor 2 2 WTDAT WTCNT Watchdog Timer operation based on the value of watchdog timer count WTCNT register Once timer is operated count value will be down counting from the initia...

Page 281: ...ug mode using Embedded ICE the watchdog timer must not operate The watchdog timer can determine whether or not it is currently in the debug mode from the CPU core signal DBGACK signal Once the DBGACK signal in CPU core is asserted the reset output of the watchdog timer is not activated as the watchdog timer is expired ...

Page 282: ... Watchdog timer control register 0x8021 WTCON Bit Description Initial State Prescaler value 15 8 Prescaler value The valid range is from 0 to 255 28 1 0x80 Reserved 7 6 Reserved These two bits must be 00 in normal operation 00 Watchdog timer 5 Enable or disable bit of Watchdog timer 0 Disable 1 Enable 1 Clock select 4 3 Determine the clock division factor 00 16 01 32 10 64 11 128 00 Interrupt gene...

Page 283: ...ister 0x8000 WTDAT Bit Description Initial State Count reload value 15 0 Watchdog timer count value for reload 0x8000 3 3 WATCHDOG TIMER COUNT WTCNT REGISTER The WTCNT register contains the current count values for the watchdog timer during normal operation Note that the content of the WTDAT register cannot be automatically loaded into the timer count register when the watchdog timer is enabled in...

Page 284: ...WATCHDOG TIMER S3C2416X RISC MICROPROCESSOR 11 6 NOTES ...

Page 285: ...own counter value This double buffering feature of TCNTBn and TCMPBn makes the timer generate a stable output when the frequency and duty ratio are changed Each timer has its own 16 bit internal down counter which is driven by the timer clock When the internal down counter reaches zero the timer interrupt request is generated to inform the CPU that the timer operation has been completed When the t...

Page 286: ... 1 8 1 16 TCLK 1 2 8 Bit Prescaler 1 4 1 8 1 16 TCLK 1 2 5 1 MUX TCMPB0 TCNTB0 Control Logic0 Dead Zone Generator Dead Zone TCMPB1 TCNTB1 Control Logic1 Dead Zone 5 1 MUX 5 1 MUX Control Logic2 TCMPB2 TCNTB2 5 1 MUX 5 1 MUX TCMPB3 TCNTB3 Control Logic3 TOUT3 TCNTB4 Control Logic4 Figure 12 1 16 bit PWM Timer Block Diagram ...

Page 287: ...scaler 0 Maximum Resolution prescaler 255 Min Interval TCNTBn 1 Max Interval TCNTBn 65535 1 2 PCLK 50 MHz 0 0400 us 25 000 MHz 10 2400 us 97 6562 kHz 0 0800 us 0 6710 sec 1 4 PCLK 50 MHz 0 0800 us 12 500 MHz 20 4800 us 48 8281 kHz 0 1600 us 1 3421 sec 1 8 PCLK 50 MHz 0 1600 us 6 250 MHz 40 9601 us 24 4140 kHz 0 3200 us 2 6843 sec 1 16 PCLK 50 MHz 0 3200 us 3 125 MHz 81 9188 us 12 2070 kHz 0 6400 u...

Page 288: ... at intervals 3cycle of TOUTn set TCNTBn TCMPBn and TCON register like Figure 12 2 That is i Set TCNTBn 3 and TCMPBn 1 ii Set auto reload 1 and manual update 1 When manual update bit is 1 TCNTBn and TCMPBn value are loaded to TCNTn and TCMPn iii Set TCNTBn 2 and TCMPBn 0 for next operation iv Set auto reload 1 and manual update 0 If you set manual update 1 at this time TCNTn is changed to 2 and TC...

Page 289: ...servation register TCNTOn If the TCNTBn is read the read value does not indicate the current state of the counter but the reload value for the next timer duration The auto reload operation copies the TCNTBn into TCNTn when the TCNTn reaches 0 The value written into the TCNTBn is loaded to the TCNTn only when the TCNTn reaches 0 and auto reload is enabled If the TCNTn becomes 0 and the auto reload ...

Page 290: ...n 2 Set the manual update bit of the corresponding timer It is recommended that you configure the inverter on off bit Whether use inverter or not 3 Set start bit of the corresponding timer to start the timer and clear the manual update bit configure the inverter on off bit as you want If the timer is stopped by force the TCNTn retains the counter value and is not reloaded from TCNTBn If a new valu...

Page 291: ...of the TCMPn the logic level of the TOUTn is changed from low to high 4 When the TCNTn reaches 0 the interrupt request is generated and TCNTBn value is loaded into a temporary register At the next timer tick the TCNTn is reloaded with the temporary register value TCNTBn 5 In Interrupt Service Routine ISR the TCNTBn and the TCMPBn are set to 80 20 60 and 60 respectively for the next duration 6 When...

Page 292: ... can be implemented by using the TCMPBn PWM frequency is determined by TCNTBn Figure 12 5 shows a PWM value determined by TCMPBn For a higher PWM value decrease the TCMPBn value For a lower PWM value increase the TCMPBn value If an output inverter is enabled the increment decrement may be reversed The double buffering function allows the TCMPBn for the next PWM cycle written at any point in the cu...

Page 293: ...assume the inverter is off 1 Turn off the auto reload bit And then the timer is stopped after the TCNTn reaches 0 TOUTn goes to high level recommended 2 Stop the timer by clearing the timer start stop bit to 0 If TCNTn TCMPn at that moment the output level is high If TCNTn TCMPn the output level is low 3 The TOUTn can be inverted by the inverter on off bit in TCON The inverter removes the addition...

Page 294: ... switching devices from being turned on simultaneously even for a very short time TOUT0 is the PWM output nTOUT0 is the inversion of the TOUT0 If the dead zone is enabled the output wave form of TOUT0 and nTOUT0 will be TOUT0_DZ and nTOUT0_DZ respectively nTOUT0_DZ is routed to the TOUT1 pin In the dead zone interval TOUT0_DZ and nTOUT0_DZ can never be turned on simultaneously TOUT0 nTOUT0 TOUT0_D...

Page 295: ...n TCFG1 register If one of timers is configured as DMA request mode that timer does not generate an interrupt request The others can generate interrupt normally DMA mode configuration and DMA interrupt operation DMA Mode DMA Request Timer0 INT Timer1 INT Timer2 INT Timer3 INT Timer4 INT 0000 No select ON ON ON ON ON 0001 Timer0 OFF ON ON ON ON 0010 Timer1 ON OFF ON ON ON 0011 Timer2 ON ON OFF ON O...

Page 296: ... Description Reset Value TCFG0 0x51000000 R W Configures the two 8 bit prescalers 0x00000000 TCFG0 Bit Description Initial State Reserved 31 24 0x00 Dead zone length 23 16 These 8 bits determine the dead zone length The 1 unit time of the dead zone length is equal to that of timer 0 0x00 Prescaler 1 15 8 These 8 bits determine prescaler value for Timer 2 3 and 4 0x00 Prescaler 0 7 0 These 8 bits d...

Page 297: ...K 0000 MUX 2 11 8 Select MUX input for PWM Timer2 0000 1 2 0001 1 4 0010 1 8 0011 1 16 01xx External TCLK 0000 MUX 1 7 4 Select MUX input for PWM Timer1 0000 1 2 0001 1 4 0010 1 8 0011 1 16 01xx External TCLK 0000 MUX 0 3 0 Select MUX input for PWM Timer0 0000 1 2 0001 1 4 0010 1 8 0011 1 16 01xx External TCLK 0000 Notice When you use External TCLK duty of TOUT may show slight error External TCLK ...

Page 298: ...ation 1 Update TCNTB3 TCMPB3 0 Timer 3 start stop 16 Determine start stop for Timer 3 0 Stop 1 Start for Timer 3 0 Timer 2 auto reload on off 15 Determine auto reload on off for Timer 2 0 One shot 1 Interval mode auto reload 0 Timer 2 output inverter on off 14 Determine output inverter on off for Timer 2 0 Inverter off 1 Inverter on for TOUT2 0 Timer 2 manual update note 13 Determine the manual up...

Page 299: ...oad on off for Timer 0 0 One shot 1 Interval mode auto reload 0 Timer 0 output inverter on off 2 Determine the output inverter on off for Timer 0 0 Inverter off 1 Inverter on for TOUT0 0 Timer 0 manual update note 1 Determine the manual update for Timer 0 0 No operation 1 Update TCNTB0 TCMPB0 0 Timer 0 start stop 0 Determine start stop for Timer 0 0 Stop 1 Start for Timer 0 0 NOTE The bit has to b...

Page 300: ...scription Initial State Timer 0 compare buffer register 15 0 Set compare buffer value for Timer 0 0x00000000 TCNTB0 Bit Description Initial State Timer 0 count buffer register 15 0 Set count buffer value for Timer 0 0x00000000 3 5 TIMER 0 COUNT OBSERVATION REGISTER TCNTO0 Register Address R W Description Reset Value TCNTO0 0x51000014 R Timer 0 count observation register 0x00000000 TCNTO0 Bit Descr...

Page 301: ...scription Initial State Timer 1 compare buffer register 15 0 Set compare buffer value for Timer 1 0x00000000 TCNTB1 Bit Description Initial State Timer 1 count buffer register 15 0 Set count buffer value for Timer 1 0x00000000 3 7 TIMER 1 COUNT OBSERVATION REGISTER TCNTO1 Register Address R W Description Reset Value TCNTO1 0x51000020 R Timer 1 count observation register 0x00000000 TCNTO1 Bit Descr...

Page 302: ...scription Initial State Timer 2 compare buffer register 15 0 Set compare buffer value for Timer 2 0x00000000 TCNTB2 Bit Description Initial State Timer 2 count buffer register 15 0 Set count buffer value for Timer 2 0x00000000 3 9 TIMER 2 COUNT OBSERVATION REGISTER TCNTO2 Register Address R W Description Reset Value TCNTO2 0x5100002C R Timer 2 count observation register 0x00000000 TCNTO2 Bit Descr...

Page 303: ...scription Initial State Timer 3 compare buffer register 15 0 Set compare buffer value for Timer 3 0x00000000 TCNTB3 Bit Description Initial State Timer 3 count buffer register 15 0 Set count buffer value for Timer 3 0x00000000 3 11 TIMER 3 COUNT OBSERVATION REGISTER TCNTO3 Register Address R W Description Reset Value TCNTO3 0x51000038 R Timer 3 count observation register 0x00000000 TCNTO3 Bit Desc...

Page 304: ...TCNTB4 Bit Description Initial State Timer 4 count buffer register 15 0 Set count buffer value for Timer 4 0x00000000 3 13 TIMER 4 COUNT OBSERVATION REGISTER TCNTO4 Register Address R W Description Reset Value TCNTO4 0x51000040 R Timer 4 count observation register 0x00000000 TCNTO4 Bit Description Initial State Timer 4 observation register 15 0 Set count observation value for Timer 4 0x00000000 ...

Page 305: ...minute hour date day month and year The RTC unit works with an external 32 768 KHz crystal and can perform the alarm function 1 1 FEATURES The Real Time Clock includes the following features BCD number second minute hour date day month and year Leap year generator Alarm function alarm interrupt or wake up from power off mode Tick counter function tick interrupt or wake up from power off mode Year ...

Page 306: ...of each month out of 28 29 30 or 31 based on data from BCDDAY BCDMON and BCDYEAR This block considers leap year in deciding on the last date An 8 bit counter can only represent 2 BCD digits therefore it cannot decide whether 00 year the year with its last two digits zeros is a leap year or not For example it cannot discriminate between 1900 and 2000 To solve this problem the RTC block in S3C2416 h...

Page 307: ...cause of the one second deviation that was mentioned In this case the user must re read from BCDYEAR to BCDSEC if BCDSEC is zero 1 2 3 Backup Battery Operation The RTC logic can be driven by the backup battery which supplies the power through the RTCVDD pin into the RTC block even if the system power is off When the system is off the interfaces of the CPU and RTC logic must be blocked and the back...

Page 308: ... 0 03 TICsel2 0 TICSel 0 16384 2 14 0 218 0 06 TICsel2 1 TICSel 0 8192 2 13 0 219 0 12 TICsel2 2 TICSel 0 4096 2 12 0 220 0 24 TICsel2 3 TICSel 0 2048 2 11 0 221 0 49 TICsel2 6 TICSel 0 1024 2 10 0 222 0 97 TICsel2 7 TICSel 0 512 2 9 0 223 1 95 TICsel2 8 TICSel 0 256 2 8 0 224 3 90 TICsel2 4 TICSel 0 128 2 7 0 225 7 81 TICsel2 9 TICSel 0 64 2 6 0 226 15 62 TICsel2 10 TICSel 0 32 2 5 0 227 31 25 TI...

Page 309: ...e Example For 1 ms Tick interrupt generation 1st RTCCON 0 1 b1 RTC enable 2nd RTCCON 3 1 b1 RTC clock counter reset 3rd RTCCON 3 1 b0 RTC clock counter enable 4th RTCCON 8 5 4 b0011 RTC divide clock selection 5th TICNT1 6 0 7 h1 Tick counter value setting 6th TICNT0 7 1 b1 Tick counter enable ...

Page 310: ...he RTC unit oscillation at 32 768 kHz A RTC Block is used 15 22pF 5Mohm XTIRTC XTORTC XTIRTC XTORTC B RTC Block is not used 15 22pF VDD_RTC 32768Hz Figure 13 3 Main Oscillator Circuit Example 1 3 EXTERNAL INTERFACE Name Direction Description XTI Input 32 kHz RTC Oscillator Clock Input XTO Input 32 kHz RTC Oscillator Clock output ...

Page 311: ...ALMMIN 0x57000058 R W Alarm minute data Register 0x00 ALMHOUR 0x5700005C R W Alarm hour data Register 0x0 ALMDATE 0x57000060 R W Alarm date data Register 0x01 ALMMON 0x57000064 R W Alarm month data Register 0x01 ALMYEAR 0x57000068 R W Alarm year data Register 0x0 BCDSEC 0x57000070 R W BCD second Register Undefined BCDMIN 0x57000074 R W BCD minute Register Undefined BCDHOUR 0x57000078 R W BCD hour ...

Page 312: ...ime clock select2 0 clock period of 1 16384 second select 1 clock period of 1 8192 second select 2 clock period of 1 4096 second select 3 clock period of 1 2048 second select 4 clock period of 1 128 second select 5 clock period of 1 second select 6 clock period of 1 1024 second select 7 clock period of 1 512 second select 8 clock period of 1 256 second select 9 clock period of 1 64 second select 1...

Page 313: ...at TICNT2 register TICNT0 16 0 NOTE Tick time count value TICK TIME COUNT 0 x 2 8 T ICK TIME COUNT 1 TICK TIME COUNT2 x 215 Register Address R W Description Reset Value TICNT0 0x57000044 R W Tick time count register 0x00 TICNT Bit Description Initial State TICK INT ENABLE 7 Tick time interrupt enable 0 Disable 1 Enable b 0 TICK TIME COUNT 0 6 0 14 8 bits of 32 bit tick time count value b 0 1 5 3 T...

Page 314: ...LMWKUP ALMEN must be enable If compare value is year ALMEN and YEAREN must be enable If compare values are year mon date hour min and sec ALMEN YEAREN MONEN DATEEN HOUREN MINEN and SECEN must be enable Register Address R W Description Reset Value RTCALM 0x57000050 R W RTC alarm control register 0x0 RTCALM Bit Description Initial State Reserved 7 0 ALMEN 6 Alarm global enable 0 Disable 1 Enable Not...

Page 315: ...000 1 5 7 ALARM MIN Data ALMMIN Register Register Address R W Description Reset Value ALMMIN 0x57000058 R W Alarm minute data Register 0x00 ALMMIN Bit Description Initial State Reserved 7 0 6 4 BCD value for alarm minute 0 5 000 MINDATA 3 0 0 9 0000 1 5 8 ALARM HOUR Data ALMHOUR Register Register Address R W Description Reset Value ALMHOUR 0x5700005C R W Alarm hour data Register 0x0 ALMHOUR Bit De...

Page 316: ...00 DATEDATA 3 0 0 9 0001 1 5 10 ALARM MONTH Data ALMMON Register Register Address R W Description Reset Value ALMMON 0x57000064 R W Alarm month data Register 0x01 ALMMON Bit Description Initial State Reserved 7 5 00 4 BCD value for alarm month 0 1 0 MONDATA 3 0 0 9 0001 1 5 11 ALARM YEAR Data ALMYEAR Register Register Address R W Description Reset Value ALMYEAR 0x57000068 R W Alarm year data Regis...

Page 317: ...ECDATA 3 0 0 9 1 5 13 BCD MINUTE BCDMIN Register Register Address R W Description Reset Value BCDMIN 0x57000074 R W BCD minute Register Undefined BCDMIN Bit Description Initial State 6 4 BCD value for minute 0 5 MINDATA 3 0 0 9 1 5 14 BCD HOUR BCDHOUR Register Register Address R W Description Reset Value BCDHOUR 0x57000078 R W BCD hour Register Undefined BCDHOUR Bit Description Initial State Reser...

Page 318: ...ATEDATA 3 0 0 9 1 5 16 BCD DAY BCDDAY Register Register Address R W Description Reset Value BCDDAY 0x57000080 R W BCD DAY Register Undefined BCDDAY Bit Description Initial State Reserved 7 3 DAYDATA 2 0 BCD value for a day of the week 1 7 1 5 17 BCD MONTH BCDMON Register Register Address R W Description Reset Value BCDMON 0x57000084 R W BCD month Register Undefined BCDMON Bit Description Initial S...

Page 319: ...lue for year 0 9 0x0 YEARDATA 3 0 0 9 0x0 NOTE For setting BCD registers RTCEN RTCCON 0 bit must be ebable But at no setting BCD registers RTCEN must be disable for reducing power comsumption 1 5 19 TICK Counter Register Register Address R W Description Reset Value TICKCNT 0x57000090 R Internal tick time counter register 0x00 TICKCNT Bit Description Initial State TICKCNT 31 0 Internal tick counter...

Page 320: ...REAL TIME CLOCK S3C2416X RISC MICROPROCESSOR 13 16 NOTES ...

Page 321: ...eiver and a control unit as shown in Figure 14 1 The baud rate generator can be clocked by PCLK EXTUARTCLK or divided EPLL clock The transmitter and the receiver contain 64 byte FIFOs and data shifters Data is written to FIFO and then copied to the transmit shifter before being transmitted The data is then shifted out by the transmit data pin TxDn Meanwhile received data is shifted from the receiv...

Page 322: ...mode Transmit Holding Register Non FIFO mode Receive FIFO Register FIFO mode Receive Holding Register Non FIFO mode only In FIFO mode all 64 Byte of Buffer register are used as FIFO register In non FIFO mode only 1 Byte of Buffer register is used as Holding register Transmit Shifter Transmit Buffer Register 64 Byte Receive Shifter Receive Buffer Register 64 Byte Figure 14 1 UART Block Diagram with...

Page 323: ...Tx holding register in the case of Non FIFO mode 2 1 2 Data Reception Like the transmission the data frame for reception is also programmable It consists of a start bit 5 to 8 data bits an optional parity bit and 1 to 2 stop bits in the line control register ULCONn The receiver can detect overrun error parity error frame error and break condition each of which can set an error flag The overrun err...

Page 324: ...or more than 32 byte in case of RTS trigger level is 32byte In AFC nRTS means that its own receive FIFO is ready to receive data or not UART A TxD nCTS UART B RxD nRTS Transmission Case in UART A UART A RxD nRTS UART B TxD nCTS Reception Case in UART A Figure 14 2 UART AFC Interface NOTE UART 3 does not support AFC function because the S3C2416 has no nRTS 3 and nCTS 3 S3C2416 s AFC does not suppor...

Page 325: ... of UMCONn 0 to 1 activating nRTS and if it is equal or larger than 32 users have to set the value to 0 inactivating nRTS 3 Repeat the Step 2 Tx Operation with FIFO 1 Select transmit mode Interrupt or DMA mode 2 Check the value of UMSTATn 0 If the value is 1 activating nCTS users write the data to Tx FIFO register 3 Repeat the Step 2 2 1 5 RS 232C Interface If the user wants to connect the UART to...

Page 326: ...d as Interrupt request or polling mode In the Non FIFO mode transferring data from the transmit holding register to the transmit shifter will cause Tx interrupt under the Interrupt request and polling mode Note that the Tx interrupt is always requested whenever the number of data in the transmit FIFO is smaller than the trigger level This means that an interrupt is requested as soon as you enable ...

Page 327: ...ART receive error will not generate any error interrupt because the character which is received with an error would have not been read The error interrupt will occur once the character is read Figure 14 3 shows the UART receiving the five characters including the two errors Time Sequence Flow Error Interrupt Note 0 When no character is read out 1 A B C D and E is received 2 After A is read out The...

Page 328: ...pback bit in the UART control register UCONn 2 1 9 Infrared IR Mode The S3C2416 UART block supports infrared IR transmission and reception which can be selected by setting the Infrared mode bit in the UART line control register ULCONn Figure 14 4 illustrates how to implement the IR mode In IR transmit mode the transmit pulse comes out at a rate of 3 16 the normal serial transmit rate when the tran...

Page 329: ...C2416X RISC MICROPROCESSOR UART 14 9 Figure 14 5 Serial I O Frame Timing Diagram Normal UART Figure 14 6 Infrared Transmit Mode Frame Timing Diagram Figure 14 7 Infrared Receive Mode Frame Timing Diagram ...

Page 330: ...CLK is EXTUARTCLK or divided EPLL clock Please refer the Figure 14 3 by this effect Using UDIVSLOT which is the factor of floating point divisor you can make more accurate baud rate when UBRDIVn is 0 floating part will not be affected For example if the baud rate is 115200 bps and SRCCLK is 40 MHz UBRDIVn and UDIVSLOTn are DIV_VAL 40000000 115200 x 16 1 21 7 1 actual dividing value is 21 7 20 7 fo...

Page 331: ...ta to the receive FIFO Parameter Symbol Min Typ Max Unit PCLK speed for UART operating Baudrate is 1Mbps FPCLK 8 72 MHz PCLK speed for UART operating Baudrate is 2Mbps FPCLK 17 45 MHz PCLK speed for UART operating Baudrate is 3Mbps FPCLK 26 18 MHz 2 1 13 UART Clock speed UART Clock selection guide for 3Mbps For using 3Mbps EPLL should be either 48MHz or 96MHz Or EXTUARTCLK should be 48MHz Table 14...

Page 332: ... control register 0x00 ULCONn Bit Description Initial State Reserved 7 0 Infrared Mode 6 Determine whether or not to use the Infrared mode 0 Normal mode operation 1 Infrared Tx Rx mode 0 Parity Mode 5 3 Specify the type of parity generation and checking during UART transmit and receive operation 0xx No parity 100 Odd parity 101 Even parity 110 Parity forced checked as 1 111 Parity forced checked a...

Page 333: ...becomes empty in Non FIFO mode or reaches Tx FIFO Trigger Level in FIFO mode 0 Rx Interrupt Type 8 Interrupt request type 0 Pulse Interrupt is requested the instant Rx buffer receives the data in Non FIFO mode or reaches Rx FIFO Trigger Level in FIFO mode 0 Rx Time Out Enable 7 Enable Disable Rx time out interrupt when UART FIFO is enabled The interrupt is a receive interrupt note 2 0 Disable 1 En...

Page 334: ...ng 3 words time in Interrupt receive mode with FIFO the Rx interrupt will be generated receive time out and the users should check the FIFO status and read out the rest 3 If Tx DMA request signal were 0 Rx DMA request signal should be 1 They can t share request signal 0 or 1 in common UCONn 3 2 UCONn 1 0 10b 11b or 11b 10b 4 When Receive mode is enabled changing of GPIO status affect to RXD line e...

Page 335: ...e 2 7 6 Determine the trigger level of transmit FIFO 00 Empty 01 16 byte 10 32 byte 11 48 byte 00 Rx FIFO Trigger Level note 2 5 4 Determine the trigger level of receive FIFO 00 1 byte 01 8 byte 10 16 byte 11 32 byte 00 Reserved 3 0 Tx FIFO Reset 2 Auto cleared after resetting FIFO 0 Normal 1 Tx FIFO reset 0 Rx FIFO Reset 1 Auto cleared after resetting FIFO 0 Normal 1 Rx FIFO reset 0 FIFO Enable n...

Page 336: ... 16 bytes 111 When RX FIFO contains 8 bytes 000 Auto Flow Control AFC 4 0 Disable 1 Enable 0 Reserved 3 1 These bits must be 0 s 00 Request to Send 0 If AFC bit is enabled this value will be ignored In this case the S3C2416 will control nRTS automatically If AFC bit is disabled nRTS must be controlled by software 0 H level Inactivate nRTS 1 L level Activate nRTS 0 NOTES 1 UART 3 does not support A...

Page 337: ...shift register is empty 0 Not empty 1 Transmitter transmit buffer shifter register empty 1 Transmit buffer empty 1 Set to 1 automatically when transmit buffer register is empty 0 The buffer register is not empty 1 Empty In Non FIFO mode Interrupt or DMA is requested In FIFO mode Interrupt or DMA is requested when Tx FIFO Trigger Level is set to 00 Empty If the UART uses the FIFO users should check...

Page 338: ...ect 3 Set to 1 automatically to indicate that a break signal has been received 0 No break receive 1 Break receive Interrupt is requested 0 Frame Error 2 Set to 1 automatically whenever a frame error occurs during receive operation 0 No frame error during receive 1 Frame error Interrupt is requested 0 Parity Error 1 Set to 1 automatically whenever a parity error occurs during receive operation 0 No...

Page 339: ...FSTAT2 0x50008018 R UART channel 2 FIFO status register 0x00 UFSTAT3 0x5000C018 R UART channel 3 FIFO status register 0x00 UFSTATn Bit Description Initial State Reserved 15 0 Tx FIFO Full 14 Set to 1 automatically whenever transmit FIFO is full during transmit operation 0 0 byte Tx FIFO data 63 byte 1 Full 0 Tx FIFO Count 13 8 Number of data in Tx FIFO 0 Reserved 7 0 Rx FIFO Full 6 Set to 1 automa...

Page 340: ...annel 1 modem status register 0x0 UMSTAT2 0x5000801C R UART channel 2 modem status register 0x0 UMSTAT0 Bit Description Initial State Delta CTS 4 Indicate that the nCTS input to the S3C2416 has changed state since the last time it was read by CPU Refer to Figure 14 8 0 Has not changed 1 Has changed 0 Reserved 3 1 0 Clear to Send 0 0 CTS signal is not activated nCTS pin is high 1 CTS signal is acti...

Page 341: ...e TXDATAn 7 0 Transmit data for UARTn 3 10 UART RECEIVE BUFFER REGISTER HOLDING REGISTER FIFO REGISTER There are four UART receive buffer registers including URXH0 URXH1 URXH2 and URXH3 in the UART block URXHn has an 8 bit data for received data Register Address R W Description Reset Value URXH0 0x50000024 R by byte UART channel 0 receive buffer register URXH1 0x50004024 R by byte UART channel 1 r...

Page 342: ...divisior integer place register 0 UBRDIV1 0x50004028 R W Baud rate divisior integer place register 1 UBRDIV2 0x50008028 R W Baud rate divisior integer place register 2 UBRDIV3 0x5000C028 R W Baud rate divisior integer place register 3 UBRDIVn Bit Description Initial State UBRDIV 15 0 Baud rate division value of integer part When UART clock source is PCLK UBRDIVn must be more than 0 UBRDIVn 0 NOTE ...

Page 343: ...Description Initial State UDIVSLOT 15 0 Select the slot number in Table 14 4 Table 14 4 Recommended Value Table of DIVSLOTn Register Floating point part Num of 1 s UDIVSLOTn 0 0 0x0000 0000_0000_0000_0000b 0 0625 1 0x0080 0000_0000_0000_1000b 0 125 2 0x0808 0000_1000_0000_1000b 0 1875 3 0x0888 0000_1000_1000_1000b 0 25 4 0x2222 0010_0010_0010_0010b 0 3125 5 0x4924 0100_1001_0010_0100b 0 375 6 0x4A...

Page 344: ...UART S3C2416X RISC MICROPROCESSOR 14 24 NOTES ...

Page 345: ...OL OHCI REGS USB STATE CONTROL LIST PROCESSOR BLOCK ED TD REGS Cntl HCI MASTER BLOCK CONTROL ED TD_DATA 32 ED TD STATUS 32 64x8 FIFO Cntl HC_DATA 8 DF_DATA 8 APP_MDATA 32 HCM_ADR DATA 32 CONTROL STATUS CONTROL CTRL CTRL RH_DATA 8 DF_DATA 8 HCF_DATA 8 Addr 6 FIFO_DATA 8 64x8 FIFO ROOT HUB HOST SIE HSIE S M DPLL ROOT HUB HOST SIE OHCI ROOT HUB REGS PORT S M PORT S M PORT S M X V R USB 1 X V R USB 2 ...

Page 346: ...0004 HcCommonStatus 0x49000008 HcInterruptStatus 0x4900000C HcInterruptEnable 0x49000010 HcInterruptDisable 0x49000014 HcHCCA 0x49000018 Memory pointer group HcPeriodCuttentED 0x4900001C HcControlHeadED 0x49000020 HcControlCurrentED 0x49000024 HcBulkHeadED 0x49000028 HcBulkCurrentED 0x4900002C HcDoneHead 0x49000030 HcRmInterval 0x49000034 Frame counter group HcFmRemaining 0x49000038 HcFmNumber 0x4...

Page 347: ...and Full speed mode Using the standard UTMI interface and AHB interface the USB 2 0 Controller can support up to 9 Endpoints including Endpoint0 with programmable Interrupt Bulk mode 1 1 FEATURE Compliant to USB 2 0 specification Supports FS HS dual mode operation EP 0 FIFO 64 bytes EP 1 2 3 4 FIFO 512 bytes double buffering EP 5 6 7 8 FIFO 1024 bytes double buffering Convenient Debugging Support ...

Page 348: ... USB 2 0 PHY Control Block USB 1 1 Host USB 2 0 PHY External USB HOST or Device Serial Interface 2 USB 1 1 Transceiver DP DN Figure 16 1 USB2 0 Block Diagram USB2 0 Function has a AHB Slave which provides the microcontroller with read and write access to the Control and Status Registers And also Function has an AHB Master to enable the link to transfer data on the AHB The S3C2416 USB system shown ...

Page 349: ...NCTION USB Function block of S3C2416 shares USB PORT1 with USB Host block To activate USB PORT1 for USB Function see USB control registers in System Controller Guide UTMI Interface AHB Slave Interface AHB Master Interface UPH SIE UTMI FIFO BLOCK Figure 16 2 USB2 0 Function Block Diagram ...

Page 350: ...t stuffing It also provides the interface signals for USB Transceiver 5 UPH UNIVERSAL PROTOCOL HANDLER This block includes state machines and FIFO control control status register and DMA control block of each direction endpoint 6 UTMI USB 2 0 TRANSCEIVER MACROCELL INTERFACE UTMI interface block connects 16 bit data bus and control signals to USB 2 0 PHY ...

Page 351: ...rs Register Address R W Description IR 0x4980_0000 R W Index Register EIR 0x4980_0004 R W Endpoint Interrupt Register EIER 0x4980_0008 R W Endpoint Interrupt Enable Register FAR 0x4980_000C R Function Address Register EDR 0x4980_0014 R W Endpoint Direction Register TR 0x4980_0018 R W Test Register SSR 0x4980_001C R W System Status Register SCR 0x4980_0020 R W System Control Register EP0SR 0x4980_0...

Page 352: ...rite Count Register MPR 0x4980_003C R W Max Packet Register DCR 0x4980_0040 R W DMA Control Register DTCR 0x4980_0044 R W DMA Transfer Counter Register DFCR 0x4980_0048 R W DMA FIFO Counter Register DTTCR1 0x4980_004C R W DMA Total Transfer Counter1 Register DTTCR2 0x4980_0050 R W DMA Total Transfer Counter2 Register MICR 0x4980_0084 R W Master Interface Control Register MBAR 0x4980_0088 R W Memor...

Page 353: ...ld precede any other operation Register Address R W Description Reset Value IR 0x4980_0000 R W Index Register 0x00 IR Bit R W Description Initial State 31 16 Reserved 0000 15 4 Reserved Don t write to this field 0 INDEX 3 0 R W Endpoint Number Select 0 6 0000 Endpoint0 0001 Endpoint1 0010 Endpoint2 0011 Endpoint3 0100 Endpoint4 0101 Endpoint5 0110 Endpoint6 0111 Endpoint7 1000 Endpoint8 0000 ...

Page 354: ...omplished by writing 1 to the bit position where the interrupt is detected Register Address R W Description Reset Value EIR 0x4980_0004 R C Endpoint Interrupt Register 0x00 EIR Bit R W Description Initial State 31 9 Reserved 0 EP8I 8 R C Endpoint 8 Interrupt Flag 0 EP7I 7 R C Endpoint 7 Interrupt Flag 0 EP6I 6 R C Endpoint 6 Interrupt Flag 0 EP5I 5 R C Endpoint 5 Interrupt Flag 0 EP4I 4 R C Endpoi...

Page 355: ...Initial State 31 9 Reserved EP8IE 8 R W Endpoint 8 Interrupt Enable Flag 0 EP7IE 7 R W Endpoint 7 Interrupt Enable Flag 0 EP6IE 6 R W Endpoint 6 Interrupt Enable Flag 0 EP5IE 5 R W Endpoint 5 Interrupt Enable Flag 0 EP4IE 4 R W Endpoint 4 Interrupt Enable Flag 0 EP3IE 3 R W Endpoint 3 Interrupt Enable Flag 0 EP2IE 2 R W Endpoint 2 Interrupt Enable Flag 0 EP1IE 1 R W Endpoint 1 Interrupt Enable Fla...

Page 356: ...ddress of USB device Register Address R W Description Reset Value FAR 0x4980_000C R Function address register 0x0 FAR Bit R W Description Initial State 31 7 Reserved FA 6 0 R MCU can read a unique USB function address from this register The address is transferred from USB Host through set_address command 7 h0 ...

Page 357: ...it Register Address R W Description Reset Value EDR 0x4980_0014 R W Endpoint direction register 0x0 EDR Bit R W Description Initial State 31 9 Reserved EP8DS 8 R W Endpoint 8 Direction Select 0 EP7DS 7 R W Endpoint 7 Direction Select 0 EP6DS 6 R W Endpoint 6 Direction Select 0 EP5DS 5 R W Endpoint 5 Direction Select 0 EP4DS 4 R W Endpoint 4 Direction Select 0 EP3DS 3 R W Endpoint 3 Direction Selec...

Page 358: ...st mode 0 TPS 3 R W Test Packets If this bit is set the USB repetitively transmit the test packets to Host The test packets are explained in 7 1 20 of USB 2 0 specification This bit can be set when TMD bit is set 0 TKS 2 R W Test K Select If this bit is set the transceiver port enters into the high speed K state This bit can be set when TMD bit is set 0 TJS 1 R W Test J Select If this bit is set t...

Page 359: ... of SCR register is set to 1 TMERR is set to 1 when timeout error is detected 0 BSERR 13 R C Bit Stuff Error If error interrupt enable bit of SCR register is set to 1 BSERR is set to 1 when bit stuff error is detected 0 TCERR 12 R C Token CRC Error If error interrupt enable bit of SCR register is set to 1 BSERR is set to 1 when CRC error in token packet is detected 0 DCERR 11 R C Data CRC Error If...

Page 360: ...etect Handshake process is ended 0 HFRM 2 R C Host Forced Resume HFRM is set by the core in suspend state when host sends resume signaling 0 HFSUSP 1 R C Host Forced Suspend HFSUSP is set by the core when the SUSPEND signaling from host is detected 0 HFRES 0 R C Host Forced Reset HFRES is set by the core when the RESET signaling from host is detected 0 ...

Page 361: ...ved EIE 8 R W Error Interrupt Enable This bit must be set to 1 to enable error interrupt 0 SPDCEN 7 R W Speed detection Control Enable 0 Disable 1 Enable 0 SPDEN 6 R W Speed Detect End Interrupt Enable When set to 1 Speed detection interrupt is generated 0 5 Reserved 4 Should be zero 0 SPDC 3 R W Speed detection Control Software can reset Speed detection Logic through this bit This bit is used to ...

Page 362: ...the last word of a packet in FIFO has an invalid upper byte This bit is cleared automatically after the MCU reads it from the FIFO 0 5 Reserved SHT 4 R C Stall Handshake Transmitted SHT informs that STALL handshake due to stall condition is sent to Host This bit is an interrupt source This bit is cleared when the MCU writes 1 0 3 2 Reserved TST 1 R C Tx successfully received TST is set by core aft...

Page 363: ...R W EP0 control register 0x0 EP0CR Bit R W Description Initial State 31 2 Reserved ESS 1 R W Endpoint Stall Set ESS is set by MCU when it intends to send STALL handshake to Host This bit is cleared when the MCU writes 0 on it ESS is needed to be set 0 after MCU writes 1 on it 0 TZLS 0 R W Tx Zero Length Set TZLS is set by MCU when it intends to send Tx zero length data to Host TZLS is useful for c...

Page 364: ...ffer Register 0x0 EP2BR 0x4980_0068 R W EP2 Buffer Register 0x0 EP3BR 0x4980_006C R W EP3 Buffer Register 0x0 EP4BR 0x4980_0070 R W EP4 Buffer Register 0x0 EP5BR 0x4980_0074 R W EP5 Buffer Register 0x0 EP6BR 0x4980_0078 R W EP6 Buffer Register 0x0 EP7BR 0x4980_007C R W EP7 Buffer Register 0x0 EP8BR 0x4980_0080 R W EP8 Buffer Register 0x0 EP BR Bit R W Description Initial State 31 16 Reserved 15 0 ...

Page 365: ...it is cleared when the MCU writes 1 on it 0 SPT 8 R C Short Packet Received SPT informs that OUT endpoint receives short packet during OUT DMA Operation This bit is cleared when the MCU writes 1 on it 0 DOM 7 R Dual Operation Mode DOM is set when the max packet size of corresponding endpoint is equal to a half FIFO size This bit is read only Endpoint0 does not support dual mode 0 FFS 6 R C FIFO Fl...

Page 366: ... mode TPS is activated when one packet data in FIFO was successfully transferred to Host and received ACK from Host This bit should be cleared by writing 1 on it after being read by the MCU 0 RPS 0 R Rx Packet Success RPS is used for Single or Dual transfer mode RPS is activated when the FIFO has a packet data to receive RPS is automatically cleared when MCU reads all packets one or two from FIFO ...

Page 367: ...B sends NAK handshake to Host regardless of IN FIFO status 0 OUTPKTHLD 11 R W The MCU can control Rx FIFO Status through this bit If this bit is set to one USB does not accept OUT data from Host 0 The USB can accept OUT data from Host according to OUT FIFO status normal operation 1 The USB does not accept OUT data from Host 0 10 8 Reserved DUEN 7 R W Dual FIFO mode Enable 0 Dual Disable Single mod...

Page 368: ...cription Reset Value BRCR 0x4980_0034 R Byte Read Count Register 0x0 BRCR Bit R W Description Initial State 31 10 Reserved RDCNT 9 0 R FIFO Read Byte Count 9 0 RDCNT is read only The BRCR inform the amount of received data from host In 16 bit Interface RDCNT informs the amount of data in half word 16 bit unit Through the LWO bit of EP0SR the MCU can determine valid byte in last data word 10 h ...

Page 369: ...used to determine the end of TX packet Register Address R W Description Reset Value BWCR 0x4980_0038 R W Byte Write Count Register 0x0 BWCR Bit R W Description Initial State 31 10 Reserved WRCNT 9 0 R W Through BWCR the MCU must load the byte counts of a TX data packet to the core The core uses this count value to determine the end of packet The count value to this register must be less than MAXP ...

Page 370: ...x0 MPR Bit R W Description Initial State 31 11 Reserved MAXP 10 0 R W MAX Packet 10 0 The max packet size of each endpoint is determined by MAX packet register The range of max packet is from 0 to 1024 bytes 000_0000_0000 Max Packet 0 byte 000_0000_1000 Max Packet 8 bytes 000_0001_0000 Max Packet 16 bytes 000_0010_0000 Max Packet 32 bytes 000_0100_0000 Max Packet 64 bytes 000_1000_0000 Max Packet ...

Page 371: ...able 0 DMDE 3 R W Demand Mode DMA Enable This bit is used to run Demand mode DMA operation 0 Demand mode disable 1 Demand mode enable 0 TDR 2 R W Tx DMA Operation Run This bit is used to set start DMA operation for Tx Endpoint IN endpoint 0 DMA operation stop 1 DMA operation run 0 RDR 1 R W Rx DMA Operation Run This bit is used to start DMA operation for Rx Endpoint OUT endpoint This bit is automa...

Page 372: ... from MCU The counter value will be used to determine the end of TX packet Register Address R W Description Reset Value DTCR 0x4980_0044 R W DMA Transfer Counter Register 0x0 MTCR Bit R W Description Initial State 31 11 Reserved DTCR 10 0 R W To operate single mode transfer DTCR is needed to be set 11 h0002 In case of Burst mode the MCU should set max packet value 11 h0 ...

Page 373: ...in this register Register Address R W Description Reset Value DFCR 0x4980_0048 R W DMA FIFO Counter Register 0x0 MFCR Bit R W Description Initial State 31 12 Reserved DFCR 11 0 R W In case of OUT Endpoint the size value of received packet will be loaded in this register automatically when Rx DMA Run is enabled In case of IN Endpoint the MCU should set max packet value 12 h0 ...

Page 374: ...operation is ended Register Address R W Description Reset Value DTTCR1 DTTCR2 0x4980_004C 0x4980_0050 R W DMA Total Transfer Counter Register 1 2 0x0 MTTCR Bit R W Description Initial State 31 16 Reserved DTTCR 15 0 R W This register should have total byte size to be transferred using DMA Interface DMA Total Transfer Counter1 Low half word value DMA Total Transfer Counter2 High half word value The...

Page 375: ...lue DICR 0x4980_0084 R W DMA Interface Counter Register 0x0 DICR Bit R W Description Initial State Reserved 31 4 Reserved 0 RELOAD_ MBAR 4 R W Select Reload Condiion 0 Every end of Full DMA operation 1 Every Packet transfer 0 Reserved 3 2 Reserved 0 MAX_BURST 1 0 R W Max Burst Length 00 Single transfer 01 4 beat incrementing burst transfer INCR4 10 8 beat incrementing burst transfer INCR8 11 16 be...

Page 376: ...E ADDRESS REGISTER MBAR Register Address R W Description Reset Value MBAR 0x4980_0088 R W Memory Base Address Register 0x0 MBAR Bit R W Description Initial State MBAR 31 0 R W This register should have memory base address to be transferred using DMA Interface 32 h0 ...

Page 377: ...N 0x4980_0100 R W Burst DMA transfer Control 0x0 MBAR Bit R W Description Initial State Reserved 31 9 R W Reserved 000000 DMAEN 8 R W DMA enable 0 Rreserved 7 5 R W Reserved 000 TF_CLR 4 R W TX fifo clear 0 Reserved 3 1 R W Reserved 000 RF_CLR 0 R W RX fifo clear 0 8 25 BURST FIFO STATUS REGISTER FSTAT Register Address R W Description Reset Value FSTAT 0x4980_0104 R W Burst DMA transfer Status 0x0...

Page 378: ...AHB Master IF Registers Unit Counter Total Transfer Counter Control are set in initial state or Interrupt service routine AHB Master IF Registers are to be set after MCU reads all data packets from USB OUT FIFO to operate a AHB Master operation after interrupt service mode Master Interface transfers data from OUT FIFO in USB core to Memory AHB Master Operation is ended and Interrupt mode is On Fig...

Page 379: ...ke Master writes data to IN FIFO AHB Master Registers Unit Counter Total Transfer Counter Control are set in intial state or Interrupt service routine AHB Master Registers are to be set after MCU writes one packet data to USB IN FIFO to operate a AHB Master operation after interrupt service mode Master Controller writes to IN FIFO in USB Core from Memory AHB Master Operation is ended and Interrupt...

Page 380: ...USB2 0 DEVICE S3C2416X RISC MICROPROCESSOR 16 34 NOTES ...

Page 381: ...Multi master IIC bus control status register IICSTAT Multi master IIC bus Tx Rx data shift register IICDS Multi master IIC bus address register IICADD When the IIC bus is free the SDA and SCL lines should be both at High level A High to Low transition of SDA can initiate a Start condition A Low to High transition of SDA can initiate a Stop condition while SCL remains steady at High Level The Start...

Page 382: ...ERFACE S3C2416X RISC MICROPROCESSOR 17 2 PCLK Address Register SDA 4 bit Prescaler IIC Bus Control Logic IICSTAT IICCON Comparator Shift Register Shift Register IICDS Data Bus SCL Figure 17 1 IIC Bus Block Diagram ...

Page 383: ... Stop condition can terminate the data transfer A Stop condition is a Low to High transition of the SDA line while SCL is High Start and Stop conditions are always generated by the master The IIC bus gets busy when a Start condition is generated A Stop condition will make the IIC bus free When a master initiates a Start condition it should send a slave address to notify the slave device One byte o...

Page 384: ...us is operating in Master mode Each byte should be followed by an acknowledgement ACK bit The MSB bit of the serial data and addresses are always sent first NOTES 1 S Start rS Repeat Start P Stop A Acknowledge 2 From Master to Slave From Slave to Master Write Mode Format with 7 bit Addresses 0 Write Data Transferred Data Acknowledge S Slave Address 7bits R W A P DATA 1Byte A Read Mode Format with ...

Page 385: ... byte data transfer The master should generate the clock pulse required to transmit the ACK bit The transmitter should release the SDA line by making the SDA line High when the ACK clock pulse is received The receiver should also drive the SDA line Low during the ACK clock pulse so that the SDA keeps Low during the High period of the ninth SCL pulse The ACK bit transmit function can be enabled or ...

Page 386: ...ot For the purpose of evaluation is that each master should detect the address bits While each master generates the slaver address it should also detect the address bit on the SDA line because the SDA line is likely to get Low rather than to keep High Assume that one master generates a Low as first address bit while the other master is maintaining High In this case both masters will detect Low on ...

Page 387: ...d 3 Set IICSTAT to enable Serial Output Write slave address to IICDS Write 0xF0 M T Start to IICSTAT The data of the IICDS is transmitted ACK period and then interrupt is pending Write 0xD0 M T Stop to IICSTAT Write new data transmitted to IICDS Stop Clear pending bit to resume The data of the IICDS is shifted to SDA START Master Tx mode has been configured Clear pending bit Wait until the stop co...

Page 388: ...ve address is transmitted ACK period and then interrupt is pending Write 0x90 M R Stop to IICSTAT Read a new data from IICDS Stop Clear pending bit to resume SDA is shifted to IICDS START Master Rx mode has been configured Clear pending bit Wait until the stop condition takes effect END Y N Figure 17 7 Operations for Master Receiver Mode ...

Page 389: ...s IICADD and IICDS the received slave address Write data to IICDS The IIC address match interrupt is generated Clear pending bit to resume The data of the IICDS is shifted to SDA START Slave Tx mode has been configured END Matched N Y Stop Interrupt is pending N Y Figure 17 8 Operations for Slave Transmitter Mode ...

Page 390: ...C compares IICADD and IICDS the received slave address Read data from IICDS The IIC address match interrupt is generated Clear pending bit to resume SDA is shifted to IICDS START Slave Rx mode has been configured END Matched N Y Stop Interrupt is pending N Y Figure 17 9 Operations for Slave Receiver Mode ...

Page 391: ...s 0 0 1 No interrupt pending when read 2 Clear pending condition Resume the operation when write 1 1 Interrupt is pending when read 2 N A when write 0 Transmit clock value note 4 3 0 IIC Bus transmit clock prescaler IIC Bus transmit clock frequency is determined by this 4 bit prescaler value according to the following formula Tx clock IICCLK IICCON 3 0 1 Undefined NOTES 1 Interfacing with EEPROM t...

Page 392: ...ta in IICDS will be transferred automatically just after the start signal 0 Serial output 4 IIC bus data output enable disable bit 0 Disable Rx Tx 1 Enable Rx Tx 0 Arbitration status flag 3 IIC bus arbitration procedure status flag bit 0 Bus arbitration successful 1 Bus arbitration failed during serial I O 0 Address as slave status flag 2 IIC bus address as slave status flag bit 0 Cleared after re...

Page 393: ...e read any time regardless of the current serial output enable bit IICSTAT setting Slave address 7 1 Not mapped 0 XXXXXXXX 2 4 MULTI MASTER IIC BUS TRANSMIT RECEIVE DATA SHIFT IICDS REGISTER Register Address R W Description Reset Value IICDS0 0x5400000C R W IIC0 Bus transmit receive data shift register 0xXX IICDS0 IICDS1 Bit Description Initial State Data shift 7 0 8 bit data shift register for II...

Page 394: ...C0 IICLC1 Bit Description Initial State Filter enable 2 IIC bus filter enable bit When SDA port is operating as input this bit should be High This filter can prevent from occurred error by a glitch during double of PCLK time 0 Filter disable 1 Filter enable 0 SDA output delay 1 0 IIC Bus SDA line delay length selection bits SDA line is delayed as following clock time PCLK 00 0 clocks 01 5 clocks 1...

Page 395: ... 1 FEATURES 1 1 1 Primitives Line Point Drawing DDA Digital Differential Analyzer algorithm Do Not Draw Last Point support BitBLT Stretched BitBLT support Nearest sampling Memory to Screen Host to Screen Color Expansion Memory to Screen Host to Screen 1 1 2 Per pixel Operation Maximum 2040 2040 image size Window Clipping 90 180 270 X flip Y flip Rotation Totally 256 3 operand Raster Operation ROP ...

Page 396: ...the field The least significant x bits of the new field data are padded with the most significant x bits of the original field data For example if the R value in RGB_565 format is 5 b11010 it will be converted to 8 b11010110 with three LSBs padded with three MSBs 3 b110 from the original R value Note that the A field in RGBA_5551 and ARGB_1555 only has one bit so it is converted to either 8 b00000...

Page 397: ...cuted the data will be written to the designated register in one cycle otherwise the data will be stored in the FIFO and wait to be dispatched after the current rendering process completes It is user s responsibility to make sure that the data written to the FIFO do not exceed its maximum capacity User can monitor the number of data entries used in FIFO by reading FIFO_USED bits in FIFO_STAT_REG o...

Page 398: ...Line Point Drawing Line Drawing renders a line between the starting point sx sy and the ending point ex ey specified by the user If the distance of these two points along y axis is greater than that along x axis ey sy ex sx the Major Axis should be set to y axis otherwise x axis If y axis is the Major Axis the y coordinate of a pixel on the line is increased or decreased by 1 from its preceding pi...

Page 399: ... a transformation of a rectangular block of pixels Typical applications include copying the off screen pixel data to frame buffer combining to bitmap patterns by Raster Operation changing the dimension of a rectangular image and so on 4 1 4 On Screen Rendering On screen bit block transfer copies a rectangular block of pixels on screen to another position on the same screen Note that on screen rend...

Page 400: ...dinates are always rounded to the nearest This rounding may cause some problem in the boundary when users try to scale the image by integer times For example if user wants to scale the image by four times and set the X_INCR as 0 25 the source coordinates in sequence are 0 0 25 0 50 0 75 1 0 and so on However when the current source coordinate is 0 75 it is rounded to the nearest integer which is 1...

Page 401: ...destination image usually the frame buffer base address SRC_HORI_RES_REG The horizontal resolution of the source image SRC_VERT_RES_REG The vertical resolution of the source image used in YUV mode SC_HORI_RES_REG The screen resolution SRC_COLOR_MODE The color mode of the source image DEST_COLOR_MODE The color mode of the destination image BG_COLOR Background color used in the Transparent Mode and ...

Page 402: ...pansion In this example the foreground color is blue and background white and the destination image is 16 pixel wide Figure 18 6 Color Expansion 2D can render Color Expansion image in Transparent Mode In this mode the pixels with background color the corresponding bits are 0 s are discarded resulting in a transparent effect The transparent effect on Color Expansion is illustrated in Figure 18 7 in...

Page 403: ...st provides the font data through these two command registers When the host writes the first 32 bit data into CMD4_REG the rendering process starts in the host to screen mode Then the host should provide the rest of data by writing them into CMD5_REG continuously 4 2 ROTATION The pixels can be rotated around the reference point ox oy by 90 180 270 degree clockwise or perform a X axis Y axis flip a...

Page 404: ...18 10 4 2 2 Rotation Effect 0 90 180 270 X flip Y flip x dcx dcy ox oy dcx 2ox dcy ox oy dcx dcx 2ox y dcy dcx ox oy dcy 2oy dcx ox oy dcy 2oy dcy Original image X axis flip 90 270 Y axis flip 180 FIMG 2D Figure 18 8 Rotation Example ...

Page 405: ... image and the DR min DR max values If each field R G B A of the color value falls in the range of DR min DR max this pixel is passed to the next stage otherwise discarded User can disable the stencil test on a specific field by clearing the corresponding bits in COLORKEY_CNTL Note that each field of DR_MIN and DR_MAX is 8 bit wide regardless of the source color mode setting 4 4 1 Related Register...

Page 406: ... examples on how to use the ROP value to perform the operations 1 Final Data Source Only the Source data matter so ROP Value 11110000 2 Final Data Destination Only the Destination data matter so ROP Value 11001100 3 Final Data Pattern Only the Pattern data matter so ROP Value 10101010 4 Final Data Source AND Destination ROP Value 11110000 11001100 11000000 5 Final Data Source OR Pattern ROP Value ...

Page 407: ...a value is alpha ALPHA 1 256 The internal computation of alpha blending and fading is as follows User specified alpha value ALPHA given by ALPHA_REG from 0 to 255 Alpha Blending data source ALPHA 1 destination 255 ALPHA 8 Fading data source ALPHA 1 8 fading offset Per pixel alpha blending ALPHA given by the source image from 0 to 255 Alpha Blending data source ALPHA 1 destination 255 ALPHA 8 Fadin...

Page 408: ...ter Setting Registers Resolution SRC_ RES_REG 0x0200 R W Source Image Resolution 0x0000_0000 SRC_HORI_RES_REG 0x0204 R W Source Image Horizontal Resolution 0x0000_0000 SRC_VERT_RES_REG 0x0208 R W Source Image Vertical Resolution 0x0000_0000 SC_RES_REG 0x0210 R W Screen Resolution 0x0000_0000 SC_HORI_RES _REG 0x0214 R W Screen Horizontal Resolution 0x0000_0000 SC_VERT_RES _REG 0x0218 R W Screen Ver...

Page 409: ...ing ROP_REG 0x0410 R W Raster Operation register 0x0000_0000 ALPHA_REG 0x0420 R W Alpha value Fading offset 0x0000_0000 Color FG_COLOR_REG 0x0500 R W Foreground Color Alpha register 0x0000_0000 BG_COLOR_REG 0x0504 R W Background Color register 0x0000_0000 BS_COLOR_REG 0x0508 R W Blue Screen Color register 0x0000_0000 SRC_COLOR_MODE_REG 0x0510 R W Src Image Color Mode register 0x0000_0000 DEST_COLO...

Page 410: ...nished interrupt enable If this bit is set when the graphics engine finishes the execution of current command an interrupt occurs and the INTP_CMD_FIN flag in INTC_PEND_REG will be set ACF 9 All Commands Finished interrupt enable If this bit is set when the graphics engine finishes the execution of all commands in the command FIFO an interrupt occurs and the INTP_ALL_FIN flag in INTC_PEND_REG will...

Page 411: ...Pending Register INTC_PEND_REG Register Address R W Description Reset Value INTC_PEND_REG 0x4D40800C R W Interrupt Pending Register 0x0 Field Bit Description Initial State Reserved 31 Should be set 1 Reserved 30 11 Reserved INTP_CMD_FIN 10 Current Command Finished interrupt flag Writing 1 to this bit clears this flag INTP_ALL_FIN 9 All Commands Finished interrupt flag Writing 1 to this bit clears ...

Page 412: ...rocess 0x1 ALL_FIN 9 1 Graphics engine is in idle state The graphics engine finishes the execution of all commands in the command FIFO Note that ALL_FIN CMD_FIN FIFO_USED 0 0 In the middle of rendering process or FIFO_USED is greater than 0 0x1 FIFO_OVERFLOW 8 1 Command FIFO is full no more commands can be handled 0 Command FIFO is not full 0x0 Reserved 7 FIFO_USED 6 1 The number of entries occupi...

Page 413: ... CMD1_REG Register Address R W Description Reset Value CMD1_REG 0x4D408104 W BitBLT Register 0x0 Field Bit Description Initial State Reserved 31 2 S 1 0 Nothing 1 Stretch BitBLT N 0 0 Nothing 1 Normal BitBLT 5 2 3 HOST Screen Start BitBLT Register CMD2_REG Register Address R W Description Reset Value CMD2_REG 0x4D408108 W Host to Screen Start BitBLT Register 0x0 Field Bit Description Initial State...

Page 414: ...ess R W Description Reset Value CMD4_REG 0x4D408110 W Host to Screen Start Color Expansion Register 0x0 Field Bit Description Initial State Data 31 0 Color Expansion Data Start 5 2 6 Host to Screen Continue Color Expansion Register CMD5_REG Register Address R W Description Reset Value CMD5_REG 0x4D408114 W Host to Screen Continue Color Expansion Register 0x0 Field Bit Description Initial State Dat...

Page 415: ...n number 0x0 5 3 2 Source Image Horizontal Resolution Register SRC_HORI_RES_REG Register Address R W Description Reset Value SRC_HORI_RES_REG 0x4D408204 R W Source Image Horizontal Resolution Register 0x0 Field Bit Description Initial State Reserved 31 1 0x0 HoriRes 10 0 Horizontal resolution of source image Range 1 2040 Note that in YUV mode HoriRes must be an even number 0x0 5 3 3 Source Image H...

Page 416: ... 3 5 Screen Horizontal Resolution Register SC_HORI_RES_REG Register Address R W Description Reset Value SC_HORI_RES_ REG 0x4D408214 R W Screen Horizontal Resolution Register 0x0 Field Bit Description Initial State Reserved 31 11 0x0 HoriRes 10 0 Horizontal resolution of the screen Range 1 2040 0x0 5 3 6 Screen Vertical Resolution Register SC_VERI_RES_REG Register Address R W Description Reset Valu...

Page 417: ...dow Requirement LeftCW_X RightCW_X 0x0 5 3 8 Left X Clipping Window Register CW_LT_X_REG Register Address R W Description Reset Value CW_LT_X_REG 0x4D408224 R W Left X Clipping Window Register 0x0 Field Bit Description Initial State Reserved 31 11 0x0 LeftCW_X 10 0 Left X Clipping Window Requirement LeftCW_X RightCW_X 0x0 5 3 9 Top Y Clipping Window Register CW_LT_Y_REG Register Address R W Descri...

Page 418: ...es SC_HORI_RES_REG 0x0 5 3 11 Right X Clipping Window Register CW_RB_X_REG Register Address R W Description Reset Value CW_RB_X_REG 0x4D408234 R W Right X Clipping Window Register 0x0 Field Bit Description Initial State Reserved 31 11 0x0 RightCW_X 10 0 Right X Clipping Window Requirement RightCW_X HoriRes SC_HORI_RES_REG 0x0 5 3 12 Bottom Y Clipping Window Register CW_RB_Y_REG Register Address R ...

Page 419: ...ate_0 X Range 0 2039 0x0 5 3 14 COORDINATE_0 X Register COORD0_X_REG Register Address R W Description Reset Value COORD0_X_REG 0x4D408304 R W Coordinate_0 X Register 0x0 Field Bit Description Initial State Reserved 31 11 0x0 COORD0_X 10 0 Coordinate_0 X Range 0 2039 0x0 5 3 15 COORDINATE_0 Y Register COORD0_Y_REG Register Address R W Description Reset Value COORD0_Y_REG 0x4D408308 R W Coordinate_0...

Page 420: ...X Range 0 2039 0x0 5 3 17 COORDINATE_1 X Register COORD1_X_REG Register Address R W Description Reset Value COORD1_X_REG 0x4D408314 R W Coordinate_1 X Register 0x0 Field Bit Description Initial State Reserved 31 11 0x0 COORD1_X 10 0 Coordinate_1 X Range 0 2039 0x0 5 3 18 COORDINATE_1 Y Register COORD1_Y_REG Register Address R W Description Reset Value COORD1_Y_REG 0x4D408318 R W Coordinate_1 Y Reg...

Page 421: ...X Range 0 2039 0x0 5 3 20 COORDINATE_2 X Register COORD2_X_REG Register Address R W Description Reset Value COORD2_ X_REG 0x4D408324 R W Coordinate_2 X Register 0x0 Field Bit Description Initial State Reserved 31 11 0x0 COORD2_X 10 0 Coordinate_2 X Range 0 2039 0x0 5 3 21 COORDINATE_2 Y Register COORD2_Y_REG Register Address R W Description Reset Value COORD2_ Y_REG 0x4D408328 R W Coordinate_2 Y R...

Page 422: ...X Range 0 2039 0x0 5 3 23 COORDINATE_3 X Register COORD3_X_REG Register Address R W Description Reset Value COORD3_ X_REG 0x4D408334 R W Coordinate_3 X Register 0x0 Field Bit Description Initial State Reserved 31 11 0x0 COORD3_X 10 0 Coordinate_3 X Range 0 2039 0x0 5 3 24 COORDINATE_3 Y Register COORD3_Y_REG Register Address R W Description Reset Value COORD3_ Y_REG 0x4D408338 R W Coordinate_3 Y R...

Page 423: ...ge 0 2039 0x0 5 3 26 Rotation Origin Coordinate X Register ROT_OC_X_REG Register Address R W Description Reset Value ROT_OC_X 0x4D408344 R W Rotation Origin Coordinate X Register 0x0 Field Bit Description Initial State Reserved 31 11 0x0 ROT_OC_X 10 0 X coordinate of the reference point of rotation Range 0 2039 0x0 5 3 27 Rotation Origin Coordinate Y Register ROT_OC_Y_REG Register Address R W Desc...

Page 424: ...alue ROTATE_REG 0x4D40834C R W Rotation Register 0x0 Field Bit Description Initial State Reserved 31 6 0x0 FY 5 Y flip 0x0 FX 4 X flip 0x0 R3 3 270 Rotation 0x0 R2 2 180 Rotation 0x0 R1 1 90 Rotation 0x0 R0 0 0 Rotation 0x1 If the two or more of Rn are set to 1 at the same time drawing engine operates unpredictably ...

Page 425: ...ster 0x0 Field Bit Description Initial State Reserved 31 22 0x0 X_INCR 21 0 X increment value 2 s complement 11 digit fraction 0x0 5 3 30 Y Increment Register Y_INCR_REG Register Address R W Description Reset Value Y_INCR_REG 0x4D408404 R W Y Increment Register 0x0 Field Bit Description Initial State Reserved 31 22 0x0 Y_INCR 21 0 Y increment value 2 s complement 11 digit fraction 0x0 ...

Page 426: ...Blending 3 b001 Perpixel Alpha Blending with Source Bitmap 3 b010 Alpha Blending with Alpha Register 3 b100 Fading Others Reserved Note that Perpixel Alpha Blending can only be applied on bit block transfer 0x0 T 9 0 Opaque Mode 1 Transparent Mode 0x0 Reserved 8 Reserved 0x0 ROP Value 7 0 Raster Operation Value 0x0 5 3 32 Alpha Register ALPHA_REG Register Address R W Description Reset Value ALPHA_...

Page 427: ... Register BG_COLOR_REG Register Address R W Description Reset Value BG_COLOR_REG 0x4D408504 R W Background Color Register 0x0 Field Bit Description Initial State BackgroundColor 31 0 Background Color Value The alpha field of the background color will be discarded 0x0 5 3 35 BlueScreen Color Register BS_COLOR_REG Register Address R W Description Reset Value BS_COLOR_REG 0x4D408508 R W BlueScreen Co...

Page 428: ...e drawing mode and color expansion mode 0x0 Color Setting 2 0 3 b000 RGB_565 3 b001 RGBA_5551 3 b010 ARGB_1555 3 b011 RGBA_8888 3 b100 ARGB_8888 3 b101 XRGB_8888 3 b110 RGBX_8888 The Color Setting is ignored if YUV mode is selected 0x0 5 3 37 Destination Image Color Mode Register DEST_COLOR_MODE_REG Register Address R W Description Reset Value DEST_COLOR_ MODE_REG 0x4D408514 R W Destination Image ...

Page 429: ...ial State Reserved 31 19 0x0 POffsetY 18 16 Pattern OffsetY Value 0x0 Reserved 15 3 0x0 POffsetX 2 0 Pattern OffsetX Value 0x0 5 3 40 Pattern Offset X Register PATOFF_X_REG Register Address R W Description Reset Value PATOFF_X_REG 0x4D408704 R W Pattern Offset X Register 0x0 Field Bit Description Initial State Reserved 31 3 0x0 POffsetX 2 0 Pattern OffsetX Value 0x0 5 3 41 Pattern Offset Y Registe...

Page 430: ...lue 1 Stencil Test On for R value 0x0 StencilOnG 2 0 Stencil Test Off for G value 1 Stencil Test On for G value 0x0 StencilOnB 1 0 Stencil Test Off for B value 1 Stencil Test On for B value 0x0 StencilOnA 0 0 Stencil Test Off for A value 1 Stencil Test On for A value 0x0 5 3 43 Colorkey Decision Reference Minimum Register COLORKEY_DR_MIN_REG Register Address R W Description Reset Value COLORKEY_DR...

Page 431: ...value 0xF Image Base Address 5 3 45 Source Image Base Address Register SRC_BASE_ADDR_REG Register Address R W Description Reset Value SRC_BASE_ ADDR_REG 0x4D408730 R W Source Image Base Address Register 0x0 Field Bit Description Initial State ADDR 31 0 Base address of the source image 0x0 5 3 46 Destination Image Base Address Register DEST_BASE_ADDR_REG Register Address R W Description Reset Value...

Page 432: ...2D S3C2416X RISC MICROPROCESSOR 18 38 NOTES ...

Page 433: ...ally and received shifted in serially HS_SPI supports the protocols for National Semiconductor Microwire and Motorola Serial Peripheral Interface 2 FEATURES The features of the HS_SPI are Supports full duplex 8 16 32 bit shift register for TX RX 8 bit prescale logic 3 clock source Supports 8bit 16bit 32bit bus interface Supports the Motorola HS_SPI protocol and National Semiconductor Microwire Two...

Page 434: ...from master output port Data are received from master through this port when in slave mode Channel 0 PSS0 Inout As to be slave selection signal all data TX RX sequences are executed when PSS0 is low 4 OPERATION The HS_SPI in S3C2416x transfers 1 bit serial data between S3C2416x and external device The HS_SPI in S3C2416x supports that CPU or DMA can access to transmit or receive FIFOs separately an...

Page 435: ...the number of samples in Rx FIFO is less than the threshold value in INT mode or DMA 4 burst mode and no additional data is received the remaining bytes are called trailing bytes To remove these bytes in RX FIFO internal timer and interrupt signal are used The value of internal timer can be set up to 1024 clocks based on APB BUS clock When timer value is to be zero interrupt signal is occurred and...

Page 436: ... 1 CPHA 1 Format B Cycle MOSI 1 2 3 4 5 6 7 8 MSB 6 5 4 3 2 1 LSB 6 5 4 3 2 1 LSB MSB SPICLK MISO MSB CPOL 1 CPHA 0 Format A Cycle MOSI 1 2 3 4 5 6 7 8 6 5 4 3 2 1 LSB 6 5 4 3 2 1 LSB SPICLK MISO LSB CPOL 0 CPHA 1 Format B Cycle MOSI 1 2 3 4 5 6 7 8 MSB 6 5 4 3 2 1 LSB 6 5 4 3 2 1 LSB MSB SPICLK MISO MSB CPOL 0 CPHA 0 Format A LSB MSB MSB MSB MSB of previous frame LSB LSB of next frame LSB LSB of ...

Page 437: ... sequence nCS manual mode 1 Set Transfer Type CPOL CPHA set 2 Set Clock configuration register 3 Set HS_SPI MODE configuration register 4 Set HS_SPI INT_EN register 5 Set Packet Count configuration register if necessary 6 Set Tx or Rx Channel on 7 Set nSSout low to start Tx or Rx operation A Set nSSout Bit to low then start TX data writing B If auto chip selection bit is set should not control nCS...

Page 438: ...pport at slave mode 1 High speed operation support at slave mode 1 b1 SW_RST 5 Software reset 0 Inactive 1 Active 1 b0 SLAVE 4 Whether HS_SPI Channel is Master or Slave 0 Master 1 Slave 1 b0 CPOL 3 Determine an active high or active low clock 0 Active high 1 Active low 1 b0 CPHA 2 Select one of the two fundamentally different transfer format 0 Format A 1 Format B 1 b0 RxChOn 1 HS_SPI Rx Channel On...

Page 439: ...urce selection to generate HS_SPI clock out 00 PCLK 01 USBCLK 10 Epll clock 11 Reserved For using USBCLK source The USB_SIG_MASK at system controller should be set to on Epll clock is from System Controller and has 4 sources MOUTEPLL DOUTMPLL PLL_SRCLK CLK27M 2 b0 ENCLK 8 Clock on off 0 Disable 1 Enable 1 b0 Prescaler Value 7 0 HS_SPI clock out division rate HS_SPI clock out Clock source 2 x Presc...

Page 440: ...d 11 Reserved 2 b0 RxTrigger 16 11 Rx FIFO trigger level in INT mode Trigger level is from 0 to 63 The value means byte number in RX FIFO 6 b0 TxTrigger 10 5 Tx FIFO trigger level in INT mode Trigger level is from 0 to 63 The value means byte number in TX FIFO 6 b0 reserved 4 3 RxDMA On 2 DMA mode on off 0 DMA mode off 1 DMA mode on 1 b0 TxDMA On 1 DMA mode on off 0 DMA mode off 1 DMA mode on 1 b0...

Page 441: ...EN Ch0 0x52000010 R W HS_SPI Interrupt Enable register 0x0 HS_SPI_INT_EN Bit Description Initial State IntEnTrailing 6 Interrupt Enable for trailing count to be zero 0 Disable 1 Enable 1 b0 IntEnRxOverrun 5 Interrupt Enable for RxOverrun 0 Disable 1 Enable 1 b0 IntEnRxUnderrun 4 Interrupt Enable for RxUnderrun 0 Disable 1 Enable 1 b0 IntEnTxOverrun 3 Interrupt Enable for TxOverrun 0 Disable 1 Enab...

Page 442: ...b0 RxFifoLvl 19 13 Data level in RX FIFO 0 7 h40 byte 7 b0 TxFifoLvl 12 6 Data level in TX FIFO 0 7 h40 byte 7 b0 RxOverrun 5 Rx Fifo overrun error 0 No error 1 Overrun error 1 b0 RxUnderrun 4 Rx Fifo underrun error 0 No error 1 Underrun error 1 b0 TxOverrun 3 Tx Fifo overrun error 0 No error 1 Overrun error 1 b0 TxUnderrun 2 Tx Fifo underrun error 0 No error 1 Underrun error If TX fifo empty alwa...

Page 443: ...Address R W Description Reset Value HS_SPI_RX_DATA Ch0 0x5200001C R HS_SPI RX DATA register 0x0 HS_SPI_RX_DATA Bit Description Initial State RX_DATA 31 0 This field contains the data to be received over the HS_SPI channel 32 b0 Register Address R W Description Reset Value Packet_Count_reg Ch0 0x52000020 R W Count how many data master gets 0x0 Packet_Count_reg Bit Description Initial State Packet_C...

Page 444: ...g Bit Description Initial State TX_underrun_clr 4 TX underrun pending clear bit 0 Non clear 1 Clear 1 b0 TX_overrun_clr 3 TX overrun pending clear bit 0 Non clear 1 Clear 1 b0 RX_underrun_clr 2 RX underrun pending clear bit 0 Non clear 1 Clear 1 b0 RX_overrun_clr 1 RX overrun pending clear bit 0 Non clear 1 Clear 1 b0 Trailing_clr 0 Trailing pending clear bit 0 Non clear 1 Clear 1 b0 ...

Page 445: ...ble 0 normal 1 swap 1 b0 TX_Half word swap 3 0 off 1 swap 1 b0 TX_Byte swap 2 0 off 1 swap 1 b0 TX_Bit swap 1 0 off 1 swap 1 b0 TX_SWAP_en 0 Swap enable 0 normal 1 swap 1 b0 Data size must be larger than swap size Register Address R W Description Reset Value FB_Clk_sel Ch0 0x5200002C R W Feedback clock selecting register 0x3 FB_Clk_sel Bit Description Initial State FB_Clk_sel 1 0 00 0ns additional...

Page 446: ...HS_SPI CONTROLLER S3C2416X RISC MICROPROCESSOR 19 14 NOTES ...

Page 447: ... compatible for SD Association s SDA Host Standard Specification We provide 2 Channel 4 bit HSMMC support 2 FEATURES SD Standard Host Spec ver 2 0 compatible SD Memory Card Spec ver 2 0 High Speed MMC Spec 4 2 compatible SDIO Card Spec Ver 1 0 compatible 512 bytes FIFO for data Tx Rx 48 bit Command Register 136 bit Response Register CPU Interface and DMA data transfer mode 1bit 4bit mode switch su...

Page 448: ...R R SDCLK Domain HCLK Domain System Bus AHB CMD ARG G Control Status AHB slave I F DMA controller AHB master FIFO DATA packet Status Control CMDRSP packet Status Control RSP Line Control Pad I F INTREQ BaseCLK Clock Control DPSRAM Control Figure 20 1 HSMMC Block Diagram ...

Page 449: ...TACARDNS in the Normal Interrupt Status Enable register Card Insertion Signal Enable ENSIGCARDNS in the Normal Interrupt Signal Enable register Card Removal Status Enable ENSTACARDREM in the Normal Interrupt Status Enable register Card Removal Signal Enable ENSIGCARDREM in the Normal Interrupt Signal Enable register 2 When the Host Driver detects the card insertion or removal clear its interrupt s...

Page 450: ...interrupt from a SD card in 4 bit mode 1 Calculate a divisor to determine SD Clock frequency by reading Base Clock Frequency for SD Clock in the Capabilities register If Base Clock Frequency for SD Clock is 00 0000b the Host System shall provide this information to the Host Driver by another method 2 Set Internal Clock Enable ENINTCLK and SDCLK Frequency Select in the Clock Control register in acc...

Page 451: ...on is occurring on the SD Bus namely when either Command Inhibit DAT or Command Inhibit CMD in the Present State register is set to 1 1 Set SD Clock Enable ENSDCLK in the Clock Control register to 0 Then the Host Controller stops supplying the SD Clock 4 4 SD CLOCK FREQUENCY CHANGE SEQUENCE START SD Clock Stop SD Clock Supply END 1 2 Figure 20 5 SD Clock Change Sequence The sequence for changing S...

Page 452: ...aximum voltage that the Host Controller supports 3 Set SD Bus Power PWRON in the Power Control register to 1 4 Get the OCR value of all function internal of SD card 5 Judge whether SD Bus voltage needs to be changed or not In case where SD Bus voltage needs to be changed go to step 6 In case where SD Bus voltage does not need to be changed go to End 6 Set SD Bus Power in the Power Control register...

Page 453: ...rrupts that may occur while changing the bus width 2 In case of SD memory only card go to step 4 In case of other card go to step 3 3 Set IENM of the CCCR in a SDIO or SD combo card to 0 by CMD52 4 Change the bit mode for a SD card Changing SD memory card bus width by ACMD6 Set bus width and changing SDIO card bus width by setting Bus Width of Bus Interface Control register in CCCR 5 In case of ch...

Page 454: ...ith the value from step 1 above 4 8 SD TRANSACTION GENERATION This section describes the sequences how to generate and control various kinds of SD transactions SD transactions are classified into three cases 1 Transactions that do not use the DAT line 2 Transactions that use the DAT line only for the busy signal 3 Transactions that use the DAT line for transferring data In this specification the f...

Page 455: ...S3C2416X RISC MICROPROCESSOR HSMMC CONTROLLER 20 9 4 9 SD COMMAND ISSUE SEQUENCE Figure 20 9 Timeout Setting Sequence ...

Page 456: ...Command Complete Interrupt has occurred go to step 2 2 Write 1 to Command Complete STACMDCMPLT in the Normal Interrupt Status register to clear this bit 3 Read the Response register and get necessary information in accordance with the issued command 4 Judge whether the command uses the Transfer Complete Interrupt or not If it uses Transfer Complete go to step 5 If not go to step 7 5 Wait for the T...

Page 457: ...mmand Complete Status Get Response Data Command with Transfer Complete Int Wait for Transfer Complete Int Clr Transfer Complete Status Transfer Complete Int occur Check Response Data no No error Return Status No Error Return Status Response Contents Error Error END 1 2 3 4 5 6 7 8 9 Figure 20 10 Command Complete Sequence ...

Page 458: ... is specified 1 Single Block Transfer The number of blocks is specified to the Host Controller before the transfer The number of blocks specified is always one 2 Multiple Block Transfer The number of blocks is specified to the Host Controller before the transfer The number of blocks specified shall be one or more 3 Infinite Block Transfer The number of blocks is not specified to the Host Controlle...

Page 459: ... Ready Int occur Clr Buffer Write Ready Status Set Block Data More Blocks write read 9 10 W 11 W 12 W 13 W yes no Wait for Buffer Read Ready Int Buffer Read Ready Int occur Clr Buffer Read Ready Status Get Block Data 11 R 12 R 10 R More Blocks yes 13 R no Single Multi Infinite Block Transfer Single or Multi block transfer Infinite block transfer Wait for Transfer Complete Int Abort Transaction Clr...

Page 460: ...o to step 10 W In case of read from a card go to step 10 R 10 W And then wait for Buffer Write Ready Interrupt 11 W Write 1 to the Buffer Write Ready STABUFWTRDY in the Normal Interrupt Status register for clearing this bit 12 W Write block data in according to the number of bytes specified at the step 1 to Buffer Data Port register 13 W Repeat until all blocks are sent and then go to step 14 10 R...

Page 461: ...sponding to the executed data byte length of one block in the Block Size register 3 Set the value corresponding to the executed data block count in the Block Count register BLKCNT 4 Set the value corresponding to the issued command in the Argument register ARGUMENT 5 Set the values for Multi Single Block Select and Block Count Enable And at this time set the value corresponding to the issued comma...

Page 462: ... 6 can also be executed simultaneously 4 12 ABORT TRANSACTION An abort transaction is performed by issuing CMD12 for a SD memory card and by issuing CMD52 for a SDIO card There are two cases where the Host Driver needs to do an Abort Transaction The first case is when the Host Driver stops Infinite Block Transfers The second case is when the Host Driver stops transfers while a Multiple Block Trans...

Page 463: ...RW1C Read only status Write 1 to clear status Register bits indicate status when read a set bit indicating a status event may be cleared by writing a 1 Writing a 0 to RW1C bits has no effect RWAC Read Write automatic clear register The Host Driver requests a Host Controller operation by setting the bit The Host Controllers shall clear the bit automatically when the operation of complete Writing a ...

Page 464: ...topped Read operations during transfers may return an invalid value The Host Driver shall initialize this register before starting a DMA transaction After DMA has stopped the next system address of the next contiguous data position can be read from this register The DMA transfer waits at the every boundary specified by the Host SDMA Buffer Boundary in the Block Size register The Host Controller ge...

Page 465: ...nsfer shall wait at the every boundary specified by these fields and the Host Controller generates the DMA Interrupt to request the Host Driver to update the System Address register In case of this register is set to 0 buffer size 4K bytes lower 12 bit of byte address points data in the contiguous buffer and the upper 20 bit points the location of the buffer in the system memory The DMA transfer s...

Page 466: ... Values ranging from 1 up to the maximum buffer size can be set In case of memory it shall be set up to 512 bytes It can be accessed only if no transaction is executing i e after a transaction has stopped Read operations during transfers may return an invalid value and write operations shall be ignored 0200h 512 Bytes 01FFh 511 Bytes 0004h 4 Bytes 0003h 3 Bytes 0002h 2 Bytes 0001h 1 Byte 0000h No ...

Page 467: ...alue between 1 and the maximum block count The Host Controller decrements the block count after each block transfer and stops when the count reaches zero Setting the block count to 0 results in no data blocks being transferred This register should be accessed only when no transaction is executing i e after transactions are stopped During data transfer read operations on this register may return an...

Page 468: ... W Description Reset Value ARGUMENT0 0X4AC00008 R W Command Argument Register Channel 0 0x0 ARGUMENT1 0X4A800008 R W Command Argument Register Channel 1 0x0 Name Bit Description Initial Value ARGUMENT 31 0 Command Argument The SD Command Argument is specified as bit39 8 of Command Format in the SD Memory Card Physical Layer Specification 0 ...

Page 469: ... 00 No CCS Operation Normal operation Not CE ATA mode 01 Read or Write data transfer CCS enable Only CE ATA mode 10 Without data transfer CCS enable Only CE ATA mode 11 Abort Completion Signal ACS generation Only CE ATA mode 0 7 6 Reserved 0 MUL1SIN0 5 Multi Single Block Select This bit enables multiple block DAT line data transfers For any other commands this bit shall be set to 0 If this bit is ...

Page 470: ...d as indicated in the DMA Support in the Capabilities register If DMA is not supported this bit is meaningless and shall always read 0 If this bit is set to 1 a DMA operation shall begin when the Host Driver writes to the upper byte of Command register 00Fh 1 Enable 0 Disable 0 Table below shows the summary of how register settings determine types of data transfer Table 20 1 Determination of Trans...

Page 471: ...pend Command If the Suspend command succeeds the Host Controller shall assume the SD Bus has been released and that it is possible to issue the next command which uses the DAT line The Host Controller shall de assert Read Wait for read transactions and stop checking busy for write transactions The interrupt cycle shall start in 4 bit mode If the Suspend command fails the Host Controller shall main...

Page 472: ...nd Index Error If this bit is set to 0 the Index field is not checked 1 Enable 0 Disable ENCMDCR C 3 Command CRC Check Enable If this bit is set to 1 the Host Controller shall check the CRC field in the response If an error is detected it is reported as a Command CRC Error If this bit is set to 0 the CRC field is not checked The number of bits checked by the CRC field value changes according to th...

Page 473: ...l 1 0x0 RSPREG1_1 0X4A800014 ROC Response Register 1 Channel 1 0x0 RSPREG2_1 0X4A800018 ROC Response Register 2 Channel 1 0x0 RSPREG3_1 0X4A80001C ROC Response Register 3 Channel 1 0x0 Name Bit Description Initial Value CMDRSP 127 0 Command Response The Table below describes the mapping of command responses from the SD Bus to this register for each response type In the table R refers to a bit rang...

Page 474: ... Enable bits in the Command register and generate an error interrupt if an error is detected The bit range for the CRC check depends on the response length If the response length is 48 the Host Controller shall check R 47 1 and if the response length is 136 the Host Controller shall check R 119 1 Since the Host Controller may have a multiple block data DAT line transfer executing concurrently with...

Page 475: ...Address R W Description Reset Value BDATA0 0X4AC00020 R W Buffer Data Register Channel 0 BDATA1 0X4A800020 R W Buffer Data Register Channel 1 Name Bit Description Initial Value BUFDAT 31 0 Buffer Data The Host Controller buffer can be accessed through this 32 bit Data Port register Detailed documents are to be copied from SD Host Standard Spec ...

Page 476: ... State PRNTWP 19 Write Protect Switch Pin Level RO The Write Protect Switch is supported for memory and combo cards This bit reflects the SDWP pin 1 Write enabled SDWP 1 0 Write protected SDWP 0 Note SDWP port is fixed to High 1 PRNTCD 18 Card Detect Pin Level RO This bit reflects the inverse value of the SDCD pin Debouncing is not performed on this bit This bit may be valid when Card State Stable...

Page 477: ...ed DIFF4W 13 FIFO Pointer Difference 4 Word ROC When the difference of the address pointer between AHB side and SD side is more than or equal to 4 word this status bit is set to HIGH When others clears automatically Write Tx mode when this bit is HIGH more than or equal to 4 word can be written by CPU side Read Rx mode when this bit is HIGH more than or equal to 4 word can be read by CPU side 0 DI...

Page 478: ...ck length is transferred to the System 2 When all valid data blocks have been transferred to the System and no current block transfers are being sent as a result of the Stop At Block Gap Request being set to 1 A Transfer Complete interrupt is generated when this bit changes to 0 1 Transferring data 0 No valid data 0 WTTRANACT 8 Write Transfer Active ROC This status indicates a write transfer is ac...

Page 479: ...r current block gap by continuing to drive the Read Wait signal It is necessary to support Read Wait in order to use the suspend resume function b In the case of write transactions This status indicates that a write transfer is executing on the SD Bus Changes in this value from 1 to 0 generate a Transfer Complete interrupt in the Normal Interrupt Status register This bit shall be set in either of ...

Page 480: ...en if the Command Inhibit DAT is set to 1 Commands using only the CMD line can be issued if this bit is 0 Changing from 1 to 0 generates a Command Complete interrupt in the Normal Interrupt Status register If the Host Controller cannot issue the command because of a command conflict error Refer to Command CRC Error or because of Command Not Issued By Auto CMD12 Error this bit shall remain 1 and th...

Page 481: ...20 35 Figure 20 14 Timing of Command Inhibit DAT and Command Inhibit CMD with data transfer Figure 20 15 Timing of Command Inhibit DAT for the case of response with busy Figure 20 16 Timing of Command Inhibit CMD for the case of no response command ...

Page 482: ...is selected 01 Reserved 10 32 bit Address ADMA2 is selected 11 64 bit Address ADMA2 is selected Not supported 0 ENHIGHSPD 2 High Speed Enable This bit is optional Before setting this bit the Host Driver shall check the High Speed Support in the Capabilities register If this bit is set to 0 default the Host Controller outputs CMD line and DAT lines at the falling edge of the SD Clock up to 25MHz If...

Page 483: ...ts the voltage level for the SD card Before setting this register the Host Driver shall check the Voltage Support bits in the Capabilities register If an unsupported voltage is selected the Host System shall not supply SD Bus voltage 111b 3 3V Typ 110b 3 0V Typ 101b 1 8V Typ 100b 000b Reserved 0 PWRON 0 SD Bus Power Before setting this bit the SD Host Driver shall set SD Bus Voltage Select If the ...

Page 484: ...t protocol to stop read data using the DAT 2 line Otherwise the Host Controller has to stop the SD Clock to hold read data which restricts commands generation When the Host Driver detects an SD card insertion it shall set this bit according to the CCCR of the SDIO card If the card does not support read wait this bit shall never be set to 1 otherwise DAT line conflict may occur If this bit is set t...

Page 485: ...d Transfer Active Write Transfer Active DAT Line Active and Command Inhibit DAT in the Present State register Regarding detailed control of bits D01 and D00 RW 1 Stop 0 Transfer There are three cases to restart the transfer after stop at the block gap Which case is appropriate depends on whether the Host Controller issues a Suspend command or the SD card accepts the Suspend command 1 If the Host D...

Page 486: ...me Bit Description Initial Value 7 3 Reserved 0 ENWKUPREM 2 Wakeup Event Enable On SD Card Removal This bit enables wakeup event via Card Removal assertion in the Normal Interrupt Status register FN_WUS Wake Up Support in CIS does not affect this bit RW 1 Enable 0 Disable 0 ENWKUPINS 1 Wakeup Event Enable On SD Card Insertion This bit enables wakeup event via Card Insertion assertion in the Normal...

Page 487: ...3MHz Setting 00h specifies the highest frequency of the SD Clock When setting multiple bits the most significant bit is used as the divisor But multiple bits should not be set The two default divider values can be calculated by the frequency that is defined by the Base Clock Frequency For SD Clock in the Capabilities register 1 25MHz divider value 2 400kHz divider value According to the SD Physica...

Page 488: ...cleared RW 1 Enable 0 Disable 0 STBLINTCLK 1 Internal Clock Stable This bit is set to 1 when SD Clock is stable after writing to Internal Clock Enable in this register to 1 The SD Host Driver shall wait to set SD Clock Enable until this bit is set to 1 Note This is useful when using PLL for a clock oscillator that requires setup time ROC 1 Ready 0 Not Ready 0 ENINTCLK 0 Internal Clock Enable This ...

Page 489: ...ion Initial Value 7 4 Reserved 0 TIMEOUTCON 3 0 Data Timeout Counter Value This value determines the interval by which DAT line timeouts are detected Refer to the Data Timeout Error in the Error Interrupt Status register for information on factors that dictate timeout generation Timeout clock frequency will be generated by dividing the base clock SDCLK value by this value When setting this registe...

Page 490: ...DAT 2 Software Reset For DAT Line Only part of data circuit is reset DMA circuit is also reset RWAC The following registers and bits are cleared by this bit Present State register Buffer Read Enable Buffer Write Enable Read Transfer Active Write Transfer Active DAT Line Active Command Inhibit DAT Block Gap Control register Continue Request Stop At Block Gap Request Normal Interrupt Status register...

Page 491: ...e cleared to 0 During its initialization the Host Driver shall set this bit to 1 to reset the Host Controller The Host Controller shall reset this bit to 0 when capabilities registers are valid and the Host Driver can read them Additional use of Software Reset For All may not affect the value of the Capabilities registers If this bit is set to 1 the SD card shall reset itself and must be reinitial...

Page 492: ...pt If any of the bits in the Error Interrupt Status register are set then this bit is set Therefore the Host Driver can efficiently test for an error by checking this bit first This bit is read only ROC 0 No Error 1 Error 0 STAFIA3 14 FIFO SD Address Pointer Interrupt 3 Status RW1C 0 Occurred 1 Not Occurred 0 STAFIA2 13 FIFO SD Address Pointer Interrupt 2 Status RW1C 0 Occurred 1 Not Occurred 0 ST...

Page 493: ...e Present State register changes from 1 to 0 When the Host Driver writes this bit to 1 to clear this status the status of the Card Inserted in the Present State register should be confirmed Because the card detect state may possibly be changed when the Host Driver clear this bit and interrupt event may not be generated RW1C 1 Card removed 0 Card state stable or Debouncing 0 STACARDINS 6 Card Inser...

Page 494: ...us After getting CRC status at SD Bus timing 1 Transaction stopped at block gap 0 No Block Gap Event 0 STATRANCMPLT 1 Transfer Complete This bit is set when a read write transfer is completed 1 In the case of a Read Transaction This bit is set at the falling edge of Read Transfer Active Status There are two cases in which this interrupt is generated The first is when a data transfer is completed a...

Page 495: ... Auto CMD12 Refer to Command Inhibit CMD in the Present State register The table below shows that Command Timeout Error has higher priority than Command Complete If both bits are set to 1 it can be considered that the response was not received correctly Command Complete Command Timeout Error Meaning of the status 0 0 Interrupted by another factor Don t care 1 Response not received within 64 SDCLK ...

Page 496: ...tus Register In addition the Host Controller generates this Interrupt when it detects invalid descriptor data Valid 0 at the ST_FDS state ADMA Error State in the ADMA Error Status indicates that an error occurs in ST_FDS state The Host Driver may find that Valid bit is not set at the error descriptor 1 Error 0 No Error 0 STAACMDERR 8 Auto CMD12 Error Occurs when detecting that one of the bits in A...

Page 497: ...o timeout this bit is set to 1 when detecting a CRC error in the command response 2 The Host Controller detects a CMD line conflict by monitoring the CMD line when a command is issued If the Host Controller drives the CMD line to 1 level but detects 0 level on the CMD line at the next SDCLK edge then the Host Controller shall abort the command Stop driving CMD line and set this bit to 1 The Comman...

Page 498: ...and CRC Error and Command Timeout Error is shown in Table below Table 21 4 The relation between Command CRC Error and Command Timeout Error Command CRC Error Command Timeout Error Kinds of error 0 0 No Error 0 1 Response Timeout Error 1 0 Response CRC Error 1 1 CMD line conflict ...

Page 499: ...led 0 Masked 0 ENSTAFIA1 12 FIFO SD Address Pointer Interrupt 1 Status Enable 1 Enabled 0 Masked 0 ENSTAFIA0 11 FIFO SD Address Pointer Interrupt 0 Status Enable 1 Enabled 0 Masked 0 ENSTARWAIT 10 Read Wait interrupt status enable 1 Enabled 0 Masked 0 ENSTACCS 9 CCS Interrupt Status Enable 1 Enabled 0 Masked 0 ENSTACARDINT 8 Card Interrupt Status Enable If this bit is set to 0 the Host Controller ...

Page 500: ...ad Ready Status Enable 1 Enabled 0 Masked 0 ENSTABUFWTRDY 4 Buffer Write Ready Status Enable 1 Enabled 0 Masked 0 ENSTADMA 3 DMA Interrupt Status Enable 1 Enabled 0 Masked 0 ENSTABLKGAP 2 Block Gap Event Status Enable 1 Enabled 0 Masked 0 ENSTASTANSCMPLT 1 Transfer Complete Status Enable 1 Enabled 0 Masked 0 ENSTACMDCMPLT 0 Command Complete Status Enable 1 Enabled 0 Masked 0 ...

Page 501: ... Auto CMD12 Error Status Enable 1 Enabled 0 Masked 0 ENSTACURERR 7 Current Limit Error Status Enable This function is not implemented in this version 1 Enabled 0 Masked 0 ENSTADENDERR 6 Data End Bit Error Status Enable 1 Enabled 0 Masked 0 ENSTADATCRCERR 5 Data CRC Error Status Enable 1 Enabled 0 Masked 0 ENSTADATTOUTERR 4 Data Timeout Error Status Enable 1 Enabled 0 Masked 0 ENSTACMDIDXERR 3 Comm...

Page 502: ...trol error interrupts using the Error Interrupt Signal Enable register 0 ENSIGFIA3 14 FIFO SD Address Pointer Interrupt 3 Signal Enable 1 Enabled 0 Masked 0 ENSIGFIA2 13 FIFO SD Address Pointer Interrupt 2 Signal Enable 1 Enabled 0 Masked 0 ENSIGFIA1 12 FIFO SD Address Pointer Interrupt 1 Signal Enable 1 Enabled 0 Masked 0 ENSIGFIA0 11 FIFO SD Address Pointer Interrupt 0 Signal Enable 1 Enabled 0 ...

Page 503: ... 0 Masked 0 ENSIGBUFWTRDY 4 Buffer Write Ready Signal Enable 1 Enabled 0 Masked 0 ENSIGDMA 3 DMA Interrupt Signal Enable 1 Enabled 0 Masked 0 ENSIGBLKGAP 2 Block Gap Event Signal Enable 1 Enabled 0 Masked 0 ENSIGSTANSCMPLT 1 Transfer Complete Signal Enable 1 Enabled 0 Masked 0 ENSIGCMDCMPLT 0 Command Complete Signal Enable 1 Enabled 0 Masked 0 ...

Page 504: ...ADMA Error Signal Enable 1 Enabled 0 Masked 0 ENSIGACMDERR 8 Auto CMD12 Error Signal Enable 1 Enabled 0 Masked 0 ENSIGCURERR 7 Current Limit Error Signal Enable This function is not implemented in this version 1 Enabled 0 Masked 0 ENSIGDENDERR 6 Data End Bit Error Signal Enable 1 Enabled 0 Masked 0 ENSIGDATCRCERR 5 Data CRC Error Signal Enable 1 Enabled 0 Masked 0 ENSIGDATTOUTERR 4 Data Timeout Er...

Page 505: ...mmand Index error occurs in response to a command 1 Error 0 No Error 0 STACMDEBITAER 3 Auto CMD12 End Bit Error Occurs when detecting that the end bit of command response is 0 1 End Bit Error Generated 0 No Error 0 STACMDCRCAER 2 Auto CMD12 CRC Error Occurs when detecting a CRC error in the command response 1 CRC Error Generated 0 No Error 0 STACMDTOUTAER 1 Auto CMD12 Timeout Error Occurs if no re...

Page 506: ...o 0 if Auto CMD12 is issued 2 At the end bit of an Auto CMD12 response Check received responses by checking the error bits D01 D02 D03 and D04 Set to 1 if error is detected Set to 0 if error is not detected 3 Before reading the Auto CMD12 Error Status bit D07 Set D07 to 1 if there is a command cannot be issued Set D07 to 0 if there is no command to issue Timing of generating the Auto CMD12 Error a...

Page 507: ...orted 1 CAPAV30 25 Voltage Support 3 0V HWInit 1 3 0V Supported 0 3 0V Not Supported 0 CAPAV33 24 Voltage Support 3 3V HWInit 1 3 3V Supported 0 3 3V Not Supported 1 CAPASUSRES 23 Suspend Resume Support HWInit This bit indicates whether the Host Controller supports Suspend Resume functionality If this bit is 0 the Suspend and Resume mechanism are not supported and the Host Driver shall not issue e...

Page 508: ...iver use this value to calculate the clock divider value Refer to the SDCLK Frequency Select in the Clock Control register and it shall not exceed upper limit of the SD Clock frequency The supported clock range is 10MHz to 63MHz If these bits are all 0 the Host System has to get information via another method Not 0 1MHz to 63MHz 000000b Get information via another method 0 CAPATOUTUNIT 7 Timeout C...

Page 509: ... MAXCURR0 0X4AC00048 HWInit Maximum Current Capabilities Register Channel 0 0x0 MAXCURR1 0X4A800048 HWInit Maximum Current Capabilities Register Channel 1 0x0 Name Bit Description Initial Value 31 24 Reserved MAXCURR18 23 16 Maximum Current for 1 8V HWInit 0 MAXCURR30 15 8 Maximum Current for 3 0V HWInit 0 MAXCURR33 7 0 Maximum Current for 3 3V HWInit 0 This register measures current in 4mA steps ...

Page 510: ...k Enable 0 CDINVRXD3 29 Card Detect signal inversion for RX_DAT 3 0 Disable 1 Enable 0 SELCARDOUT 28 Card Removed Condition Selection 0 Card Removed condition is Not Card Insert State When the transition from Card Inserted state to Debouncing state 1 Card Removed state is Card Out State When the transition from Debouncing state to No Card state 0 FLTCLKSEL 27 24 Filter Clock iFLTCLK Selection Filt...

Page 511: ...ount Debounce Filter Count setting register for Card Detect signal input SDCD 00 No use debounce filter 01 4 iSDCLK 10 16 iSDCLK 11 64 iSDCLK 0 ENCLKOUTHOLD 8 SDCLK Hold Enable The enter and exit of the SDCLK Hold state is done by Host Controller 0 Disable 1 Enable 0 RWAITMODE 7 Read Wait Release Control 0 Read Wait state is released by the Host Controller Auto 1 Read Wait state is released by the...

Page 512: ... signal Command Data 0 2 Reserved 0 ENCLKOUTMSKCON 1 SDCLK output clock masking when Card Insert cleared This field when High is used not to stop SDCLK when No Card state 0 Disable 1 Enable 0 HWINITFIN 0 SD Host Controller Hardware Initialization Finish 0 Not Finish 1 Finish 0 NOTES 1 Ensure to always set SDCLK Hold Enable EnSCHold if the card does not support Read Wait to guarantee for Receive da...

Page 513: ...ock Select 1 Reference note 2 0x0 FIA1 14 8 FIFO Interrupt Address register 1 FIFO 512Byte Buffer memory word address unit Initial value 0x3F generates at 256 byte 64 word position 0x3F FCSEL0 7 Feedback Clock Select 0 Reference note 2 0x0 FIA0 6 0 FIFO Interrupt Address register 0 FIFO 512Byte Buffer memory word address unit Initial value 0x1F generates at 128 byte 32 word position 0x1F NOTES 1 F...

Page 514: ...ue DBGREG 31 0 Debug Register Read Only Register for Debug Purpose RO Not fixed 5 30 CONTROL REGISTER 4 Register Address R W Description Reset Value CONTROL4_0 0x4AC0008C R W Control register 4 Channel 0 0x0 CONTROL4_1 0x4A80008C R W Control register 4 Channel 1 0x0 Name Bit Description Initial Value Reserved 31 1 0 StaBusy 0 Status Busy This bit is High when the clock domain crossing HCLK to SDCL...

Page 515: ... Register can be written Writing 1 set each bit of the Auto CMD12 Error Status Register Writing 0 no effect D15 D12 Name Bit Description Initial Value 15 8 0x0 7 Force Event for Command Not Issued By Auto CMD12 Error 1 Interrupt is generated 0 No Interrupt 0 6 5 0 4 Force Event for Auto CMD12 Index Error 1 Interrupt is generated 0 No Interrupt 0 3 Force Event for Auto CMD12 End Bit Error 1 Interru...

Page 516: ...er the Error Interrupt can be set in the Error Interrupt Status register In order to generate interrupt signal both the Error Interrupt Status Enable and Error Interrupt Signal Enable shall be set Name Bit Description Initial Value 15 10 Reserved 0x0 9 Force Event for ADMA Error 1 Interrupt is generated 0 No Interrupt 0 8 Force Event for Auto CMD12 Error 1 Interrupt is generated 0 No Interrupt 0 7...

Page 517: ...e indicates that an error occurs at ST_FDS state The Host Driver may find that the Valid bit is not set in the error descriptor Register Address R W Description Reset Value ADMAERR0 0X4AC00054 R W ADMA Error Status Register Channel 0 0x00 ADMAERR1 0X4A800054 R W ADMA Error Status Register Channel 1 0x00 Name Bit Description Initial Value 31 11 Reserved 0x00 10 ADMA Final Block Transferred ROC In A...

Page 518: ...g ADMA data transfer This field never indicates 10 because ADMA never stops in this state D01 D00 ADMA Error State when error is occurred Contents of SYS_SDR register 00 ST_STOP Stop DMA Points next of the error descriptor 01 ST_FDS Fetch Descriptor Points the error descriptor 10 Never set this state Not used 11 ST_TFR Transfer Data Points the next of the error descriptor 0 ...

Page 519: ...f ADMA the Host Driver shall set start address of the Descriptor table The ADMA increments this register address which points to next line when every fetching a Descriptor line When the ADMA Error Interrupt is generated this register shall hold valid Descriptor address depending on the ADMA state The Host Driver shall program Descriptor Table on 32 bit boundary and set 32 bit boundary address to t...

Page 520: ...e Bit Description Initial Value VENVER 15 8 Vendor Version Number This status is reserved for the vendor version number The Host Driver should not use this status 0x04 SDMMC4 0 Host Controller 0x04 SPECVER 7 0 Specification Version Number This status indicates the Host Controller Spec Version The upper and lower 4 bits indicate the version 00 SD Host Specification Version 1 0 01 SD Host Specificat...

Page 521: ...vel alpha blending color key x y position control soft scrolling variable window size and etc The LCD controller can support the various requirements on the screen related to the number of horizontal and vertical pixels data line width for the data interface interface timing and refresh rate The LCD controller transfers the video data from the frame buffer and generates the necessary control signa...

Page 522: ...d color Supports 16 18 or 24 bpp non palletized color Window 1 Supports 1 2 4 or 8 bpp palletized color Supports 16 18 or 24 bpp non palletized color Configurable Burst Length Programable 4 8 16 Burst DMA Palette Look up table 256 x 25 ARGB bits palette 2ea for Window 0 Window1 Soft Scrolling Horizontal 1 Byte resloution Vertical 1 pixel resolution Virtual Screen Virtual image can has up to 1Mbyte...

Page 523: ... FLOW FIFO is present in the VDMA When FIFO is empty or partially empty VDMA requests data fetching from the frame memory based on the burst memory transfer mode Consecutive memory fetching of 4 8 16 words per one burst request without allowing the bus mastership to another bus master during the bus transfer When bus arbitrator in the memory controller accepts this kind of transfer request there w...

Page 524: ...ce One type is the conventional RGB interface that uses RGB data Vertical horizontal sync data valid signal and data sync clock The Second type is i80 System interface that uses address data chip select read write control and register status indicating signal In this type of LCD driver it has a frame buffer and has the function of self refresh so LCD controller updates one still image by writing o...

Page 525: ... examples of each display mode 2 4 2 28BPP display A4 888 BSWP 0 HWSWP 0 BLD_PIX 1 ALPHA_SEL 1 D 31 28 D 27 24 D 23 0 000H Dummy Bit Alpha value P1 004H Dummy Bit Alpha value P2 008H Dummy Bit Alpha value P3 P1 P2 P3 P4 P5 LCD Panel NOTE D 23 16 Red data D 15 8 Green data D 7 0 Blue data In case of BLD_PIX and ALPHA_SEL are set D 27 24 Alpha value D 23 16 Red data D 15 8 Green data D 7 0 Blue data...

Page 526: ... AEN P3 P1 P2 P3 P4 P5 LCD Panel NOTES 1 AEN Select Alpha value in Window 1 Alpha Value Register for alpha blending AEN 0 ALPHA0_R G B values are applied AEN 1 ALPHA1_R G B values are applied Each pixel of LCD panel displays blended color with lower layer window Refer to the equation of alpha blending on page 21 22 2 D 23 16 Red data D 15 8 Green data D 7 0 Blue data ...

Page 527: ... AEN P3 P1 P2 P3 P4 P5 LCD Panel NOTES 1 AEN Select Alpha value in Window 1 Alpha Value Register for alpha blending AEN 0 ALPHA0_R G B values are applied AEN 1 ALPHA1_R G B values are applied Each pixel of LCD panel displays blended color with lower layer window Refer to the equation of alpha blending on page 21 22 2 D 22 15 Red data D 14 7 Green data D 6 0 Blue data ...

Page 528: ...2416X RISC MICROPROCESSOR 21 8 2 4 5 24BPP display 888 BSWP 0 HWSWP 0 D 31 24 D 23 0 000H Dummy Bit P1 004H Dummy Bit P2 008H Dummy Bit P3 P1 P2 P3 P4 P5 LCD Panel NOTE D 23 16 Red data D 15 8 Green data D 7 0 Blue data ...

Page 529: ... AEN P3 P1 P2 P3 P4 P5 LCD Panel NOTES 1 AEN Select Alpha value in Window 1 Alpha Value Register for alpha blending AEN 0 ALPHA0_R G B values are applied AEN 1 ALPHA1_R G B values are applied Each pixel of LCD panel displays blended color with lower layer window Refer to the equation of alpha blending on page 21 22 2 D 17 12 Red data D 11 6 Green data D 5 0 Blue data ...

Page 530: ...CROPROCESSOR 21 10 2 4 7 18BPP display 666 BSWP 0 HWSWP 0 D 31 18 D 17 0 000H Dummy Bit P1 004H Dummy Bit P2 008H Dummy Bit P3 P1 P2 P3 P4 P5 LCD Panel P1 P2 P3 P4 P5 LCD Panel NOTE D 17 12 Red data D 11 6 Green data D 5 0 Blue data ...

Page 531: ...H AEN2 P2 AEN1 P1 004H AEN4 P4 AEN3 P3 008H AEN6 P6 AEN5 P5 P1 P2 P3 P4 P5 LCD Panel NOTES 1 AEN Select Alpha value in Window 1 Alpha Value Register for alpha blending AEN 0 ALPHA0_R G B values are applied AEN 1 ALPHA1_R G B values are applied Each pixel of LCD panel displays blended color with lower layer window Refer to the equation of alpha blending on page 21 22 2 D 14 10 Red data D 9 5 Green ...

Page 532: ... display 1 555 BSWP 0 HWSWP 0 D 31 16 D 15 0 000H P1 P2 004H P3 P4 008H P5 P6 BSWP 0 HWSWP 1 D 31 16 D 15 0 000H P2 P1 004H P4 P3 008H P6 P5 NOTE D 14 10 D 15 Red data D 9 5 D 15 Green data D 4 0 D 15 Blue data Figure 21 3 16BPP 1 5 5 5 BSWP HWSWP 0 Display Types ...

Page 533: ... 10 16BPP display 565 BSWP 0 HWSWP 0 D 31 16 D 15 0 000H P1 P2 004H P3 P4 008H P5 P6 BSWP 0 HWSWP 1 D 31 16 D 15 0 000H P2 P1 004H P4 P3 008H P6 P5 NOTE D 15 11 Red data D 10 5 Green data D 4 0 Blue data Figure 21 4 16BPP 5 6 5 BSWP HWSWP 0 Display Types ...

Page 534: ...D 7 D 6 0 000H AEN4 P4 AEN3 P3 AEN2 P2 AEN1 P1 004H AEN8 P8 AEN7 P7 AEN6 P6 AEN5 P5 008H AEN12 P12 AEN11 P11 AEN10 P10 AEN9 P9 P1 P2 P3 P4 P5 LCD Panel P6 P7 P8 P10 P11 P12 P9 NOTES 1 AEN Select Alpha value in Window 1 Alpha Value Register for alpha blending AEN 0 ALPHA0_R G B values are applied AEN 1 ALPHA1_R G B values are applied Each pixel of LCD panel displays blended color with lower layer w...

Page 535: ... P5 008H P12 P11 P10 P9 P1 P2 P3 P4 P5 LCD Panel P6 P7 P8 P10 P11 P12 P9 NOTE The values of frame buffer are index of palette memory The MSB value of Palette memory is AEN bit AEN Select Alpha value in Window 1 Alpha Value Register for alpha blending AEN 0 ALPHA0_R G B values are applied AEN 1 ALPHA1_R G B values are applied Each pixel of LCD panel displays blended color with lower layer window Re...

Page 536: ...15 12 D 11 8 D 7 4 D 3 0 000H P7 P8 P5 P6 P3 P4 P1 P2 004H P15 P16 P13 P14 P11 P12 P9 P10 008H P23 P24 P21 P22 P19 P20 P17 P18 NOTE The values of frame buffer are index of palette memory The MSB value of Palette memory is AEN bit AEN Select Alpha value in Window 1 Alpha Value Register for alpha blending AEN 0 ALPHA0_R G B values are applied AEN 1 ALPHA1_R G B values are applied Each pixel of LCD p...

Page 537: ... 002H P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 006H P33 P34 P35 P36 P37 P38 P39 P40 P41 P42 P43 P44 P45 P46 P47 P48 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 000H P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 004H P49 P50 P51 P52 P53 P54 P55 P56 P57 P58 P59 P60 P61 P62 P63 P64 NOTE The values of frame buffer are index of palette memory The MSB value of Palette memory is...

Page 538: ... 5 4 3 2 1 0 RED 5 4 3 2 1 0 GREEN 5 4 3 2 1 0 BLUE NC NC 5 4 3 2 1 0 NC 2 5 3 VD Pin Descriptions at 16BPP RGB parallel 5 6 5 VD 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RED 4 3 2 1 0 GREEN 5 4 3 2 1 0 BLUE NC NC 4 3 2 1 0 NC 2 5 4 VD Pin Descriptions at 24BPP RGB Serial 8 8 8 VD 23 22 21 20 19 18 17 16 15 0 1st time 7 6 5 4 3 2 1 0 2nd time 7 6 5 4 3 2 1 0 3rd time 7 6 5 4 3...

Page 539: ...terface VD 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RED 5 4 3 2 1 0 GREEN 5 4 3 2 1 0 BLUE NC 5 4 3 2 1 0 2 5 7 VD Pin Descriptions at 16BPP i80 System Interface VD 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RED 4 3 2 1 0 GREEN 5 4 3 2 1 0 BLUE NC 4 3 2 1 0 NC ...

Page 540: ...able 21 3 and then connect VD pin to LCD panel R 5 VD 23 19 G 5 VD 15 11 and B 5 VD 7 3 Select Alpha value in Window 1 Alpha Value Register At the last Set Window Palette Control W0PAL case window0 register to 0 b101 Table 21 1 25BPP A 8 8 8 Palette Data Format INDEX Bit Pos 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 00H AEN R7 R6 R5 R4 R3 R2 R1 R0 G7 G6 G5 G4 G3 G2 G1 G0 B7 ...

Page 541: ...G0 B5 B4 B3 B2 B1 B0 FFH AEN R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 Number of VD 23 22 21 20 19 18 15 14 13 12 15 14 7 6 5 4 3 2 Table 21 3 16BPP A 5 5 5 Palette Data Format INDEX Bit Pos 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 00H AEN R4 R3 R2 R1 R0 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0 01H AEN R4 R3 R2 R1 R0 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0 FFH AEN R4 R3 R2 R1 R0 G4 ...

Page 542: ... total system 3 1 1 Total 2 windows Window 0 base RGB with palette Window 1 overlay RGB with palette 3 1 2 Overlay Priority Win 1 Win 0 3 1 3 Blending equation WinOut R Win0 R x 1 AR Win1 R x AR WinOut G Win0 G x 1 AG Win1 G x AG WinOut B Win0 B x 1 AB Win1 B x AB Where AR Win1 s Red blending factor ALPHA0_R 16 or ALPHA1_R 16 or DATA 27 24 16 AR range is 0 1 AG Win1 s Green blending factor ALPHA0_...

Page 543: ...B ALPHA_SEL 0 WINCON1 1 KEYBLEND 1 W1KEYCON0 26 Key area ALPHA1_R G B BLD_PIX 1 WINCON1 6 ALPHA_SEL 1 WINCON1 1 DATA 27 24 in frame buffer for 28bpp mode 3 2 1 COLOR KEY FUNCTION The LCD controller can support color key function for the various effect of image mapping Color image of OSD layer which is specified by COLOR KEY register will be substituted by background image for special functionality...

Page 544: ...Match with COLVAL Unselected window Unmatched with CONVAL Selected window COMPKEY Frame Buffer R G B COLVAL Compare Figure 21 6 Color Key Block Diagram Window0 Green Window1 Red Window0 Green Key area Non Key area COLVAL 0Xff0000 Key area Match with COLVAL area Non Key area Unmatched with COLVAL area Window1 Blue Window1 Blue Figure 21 7 Color Key Operations ...

Page 545: ...21 25 No Blend and Color Key Enable Blended Alpha 0x0 OSD Image 180x100 Back Ground 320x240 Blended Alpha 0xf and No Color key Blended Alpha 0x9 and No Color key Blended Alpha 0x9 and Color Key Enable Figure 21 8 Color Key Function Configurations ...

Page 546: ...cal display size 1 The rate of RGB_VCLK signal can be controlled by the CLKVAL field in the VIDCON0 register The table below defines the relationship of RGB_VCLK and CLKVAL The minimum value of CLKVAL is 1 RGB_VCLK Hz HCLK CLKVAL 1 Table 21 5 Relation between VCLK and CLKVAL Freq of Video Clock Source 60MHz CLKVAL 60MHz X VCLK 1 60 MHz 2 30 0 MHz 2 60 MHz 3 15 0 MHz 63 60 MHz 64 938 kHz The RGB_HS...

Page 547: ...a of line 9 of virtual screen This is the data of line 10 of virtual screen This is the data of line 10 of virtual screen This is the data of line 11 of virtual screen This is the data of line 11 of virtual screen Before Scrolling View Port The same size of LCD panel LINEVAL 1 OFFSIZE PAGEWIDTH This is the data of line 1 of virtual screen This is the data of line 1 of virtual screen This is the da...

Page 548: ...cal Sync Signal RGB_VCLK Output LCD Video Clock RGB_VDEN Output Data Enable RGB_VD 23 0 Output RGB data output 6 1 2 RGB I F Timing VSPW 1 VBPD 1 LINEVAL 1 VFPD 1 1 FRAME INT_FrSyn internal RGB_VSYNC RGB_HSYNC RGB_VDEN 1 LINE HSPW 1 HBPD 1 HOZVAL 1 HFPD 1 RGB_HSYNC RGB_VCLK RGB_VD RGB_VDEN VSPW 0 VBPD 0 VFPD 0 HSPW 1 HBPD 1 HFPD 1 Figure 21 10 LCD RGB Interface Timing ...

Page 549: ...1 Signals Name Type Description SYS_VD 17 0 InOut Video Data SYS_CS0 Output Chip select for Main LCD SYS_CS1 Output Chip select for Sub LCD SYS_WR Output Write enable SYS_OE Output Output enable SYS_RS Output Register State select 7 1 2 CPU i80 System I F Timing Figure 21 11 Write Cycle Timing ...

Page 550: ..._WR 01 Reserved RGB_VCLK SYS_WR 00 RGB_VCLK 10 11 SYS_CS0 01 Reserved RGB_HSYNC SYS_CS0 00 RGB_HSYNC 10 11 SYS_CS1 01 Reserved RGB_VSYNC SYS_CS1 00 RGB_VSYNC 10 11 SYS_RS 01 Reserved RGB_VDEN SYS_RS 00 RGB_VDEN 10 11 SYS_OE 01 Reserved RGB_LEND SYS_OE 00 RGB_LEND 10 11 SYS_VD 01 Reserved RGB_VD SYS_VD 00 RGB_VD VIDOUT values are defined in VIDCON0 23 22 ...

Page 551: ...4C80000C R W Video time control 1 register 0x0000_0000 VIDTCON2 0x4C800010 R W Video time control 2 register 0x0000_0000 WINCON0 0x4C800014 R W Window control 0 register 0x0000_0000 WINCON1 0x4C800018 R W Window control 1 register 0x0000_0000 VIDOSD0A 0x4C800028 R W Video Window 0 s position control register 0x0000_0000 VIDOSD0B 0x4C80002C R W Video Window 0 s position control register 0x0000_0000...

Page 552: ..._0000 W4KEYCON0 0x4C8000C8 R W Color key control register 0x0000_0000 W4KEYCON1 0x4C8000CC R W Color key value transparent value register 0x0000_0000 WIN0MAP 0x4C8000D0 R W Window color control 0x0000_0000 WIN1MAP 0x4C8000D4 R W Window color control 0x0000_0000 WPALCON 0x4C8000E4 R W Window Palette control register 0x0000_0000 SYSIFCON0 0x4C800130 R W i80 System Interface control for Main LDI 0x00...

Page 553: ...ormat of i80 System I F Sub LDI Only when VIDOUT 2 b11 000 16 bit mode 16 bpp 001 16 2 bit mode 18 bpp 010 9 9 bit mode 18 bpp 011 16 8 bit mode 24 bpp 100 18 bit mode 18bpp 000 L0_DATA16 18 16 Select the mode of output data format of i80 System I F Main LDI Only when VIDOUT 2 b10 000 16 bit mode 16 bpp 001 16 2 bit mode 18 bpp 010 9 9 bit mode 18 bpp 011 16 8 bit mode 24 bpp 100 18 bit mode 18bpp...

Page 554: ... CLKVAL_F register 0 Direct clock frequency of VCLK frequency of Clock source 1 Divided using CLKVAL_F 0 CLKSEL_F 3 2 Select the Video Clock source 00 HCLK 01 LCD video Clock from SYSCON EPLL 10 Reserved 11 Reserved 0 ENVID 1 0 Video output and the LCD logics enable disable control 00 Disable video signals and logics immediately 01 Reserved 10 Disable video signals and logics at the end of current...

Page 555: ...SYNC 6 This bit indicates the HSYNC pulse polarity 0 normal active high 1 inverted active low 0 IVSYNC 5 This bit indicates the VSYNC pulse polarity 0 normal active high 1 inverted active low 0 IVDEN 4 This bit indicates the VDEN signal polarity 0 normal active high 1 inverted active low 0 Reserved 3 0 Reserved 0x0 8 1 5 VIDEO Time Control 0 Register Register Address R W Description Reset Value VI...

Page 556: ...he end of active data and the edge of next HSYNC Period HFPD 1 Note When the PNRMODE VIDCON0 14 13 is set to serial format the period of HFPD becomes 3 times of VCLK If HFPD is set to 0 in serial mode the period becomes 3 VLCK 0x00 HSPW 7 0 Horizontal sync pulse width determines the HSYNC pulse s level width by counting the number of the VCLK Period HSPW 1 Note When the PNRMODE VIDCON0 14 13 is se...

Page 557: ... Sytem I F supports auto change mode 0 BITSWP 18 Bit swap control bit 0 Swap Disable 1 Swap Enable 0 BYTSWP 17 Byte swaps control bit 0 Swap Disable 1 Swap Enable 0 HAWSWP 16 Half Word swap control bit 0 Swap Disable 1 Swap Enable 0 Reserved 15 11 Reserved 0 BURSTLEN 10 9 DMA s Burst Length selection 00 16 word burst 01 8 word burst 10 4 word burst 11 Reserved 0 Reserved 8 6 Reserved 0 BPPMODE_F 5...

Page 558: ... the BPP Bits Per Pixel mode Window image 0000 1bpp palletized 0001 2bpp palletized 0010 4bpp palletized 0011 8bpp palletized 0100 8bpp non palletized A 1 R 2 G 3 B 2 0101 16bpp non palletized R 5 G 6 B 5 0110 16bpp non palletized A 1 R 5 G 5 B 5 0111 16bpp non palletized I 1 R 5 G 5 B 5 1000 Unpacked 18bpp non palletized R 6 G 6 B 6 1001 Unpacked 18bpp non palletized A 1 R 6 G 6 B 5 1010 Unpacked...

Page 559: ...Description Initial State OSD_LeftTopX_F 21 11 Horizontal screen coordinate for left top pixel of OSD image 0 OSD_LeftTopY_F 10 0 Vertical screen coordinate for left top pixel of OSD image 0 8 1 11 Window 0 Position Control B Register Register Address R W Description Reset Value VIDOSD0B 0x4C80002C R W Video Window 0 s position control register 0x0000_0000 VIDOSD0B Bit Description Initial State OS...

Page 560: ...te OSD_RightBotX_F 21 11 Horizontal screen coordinate for right bottom pixel of OSD image 0 OSD_RightBotY_F 10 0 Vertical screen coordinate for right bottom pixel of OSD image 0 NOTE Registers must have word boundary X position So 24bpp mode should have X position by 1 pixel ex X 0 1 2 3 16bpp mode should have X position by 2 pixel ex X 0 2 4 6 8bpp mode should have X position by 4 pixel ex X 0 4 ...

Page 561: ... 24 of the bank location for the video buffer in the system memory 0x0 VBASEU_F 23 0 These bits indicate A 23 0 of the start address of the Video frame buffer 0x0 8 1 16 FRAME Buffer Address 1 Register Register Address R W Description Reset Value VIDW00ADD1B0 0x4C80007C R W Window 0 s buffer end address register buffer 0 0x0000_0000 VIDW00ADD1B1 0x4C800080 R W Window 0 s buffer end address registe...

Page 562: ...size register 0x0000_0000 VIDWxxADD2 Bit Description Initial State OFFSIZE_F 25 13 Virtual screen offset size the number of byte This value defines the difference between the address of the last byte displayed on the previous Video line and the address of the first byte to be displayed in the new Video line OFFSIZE_F must have value more than burst size value or 0 0 PAGEWIDTH_F 12 0 Virtual screen...

Page 563: ...t start of 00 None 01 BACK Porch 10 VSYNC 11 FRONT Porch 0 INTFRMEN 12 Video Frame interrupts SUBINT_LCD3 Enable control bit 0 Video Frame Interrupt Disable 1 Video Frame Interrupt Enable 0 FIFOSEL 11 5 FIFO Interrupt control bit each bit has the meaning of 11 7 Reserved 6 Window 1 control 0 disable 1 enable 5 Window 0 control 0 disable 1 enable 0 FIFOLEVEL 4 2 Video FIFO Interrupt SUBINT_LCD2 Lev...

Page 564: ...A0_R G B Key area ALPHA1_R G B Note This bit is meaningful when BLD_PIX is 1 and ALPHA_SEL is 0 0 KEYEN_F 25 Color Key Chroma key Enable control 0 Color key disable 1 Color key enable 0 DIRCON 24 Color key Chroma key direction control 0 If the pixel value match fore ground image with COLVAL pixel from back ground image is displayed only in OSD area 1 If the pixel value match back ground with COLVA...

Page 565: ...ect 0 NOTE COLVAL and COMPKEY use 24 bit color data at all bpp mode Unused higher bits should be 1b BPP24 mode 24 bit color value is valid A COLVAL Red COLVAL 23 16 Green COLVAL 15 8 Blue COLVAL 7 0 B COMPKEY Red COMPKEY 23 16 Green COMPKEY 15 8 Blue COMPKEY 7 0 BPP16 5 6 5 mode 16 bit color value is valid A COLVAL Red COLVAL 23 19 Green COLVAL 15 10 Blue COLVAL 7 3 B COMPKEY Red COMPKEY 23 19 Gre...

Page 566: ...op and MAPCOLOR will be appear on back ground image instead of original image 0 disable 1 enable 0 MAPCOLOR 23 0 Color Value 0 8 1 22 WIN1 Color MAP Register Address R W Description Reset Value WIN1MAP 0x4C8000D4 R W Window color control 0x0000_0000 WIN1MAP Bit Description Initial state MAPCOLEN_F 24 Window s color mapping control bit If this bit is enabled then Video DMA will stop and MAPCOLOR wi...

Page 567: ...D controller cannot access palette After update users should clear this bit for operation of palletized LCD 0 Normal Mode LCD controller access 1 Enable ARM access 0 W1PAL 5 3 This bit determines the size of the palette data format of Window 1 000 25 bit A 8 8 8 001 24 bit 8 8 8 010 19 bit A 6 6 6 011 18 bit A 6 6 5 100 18 bit 6 6 6 101 16 bit A 5 5 5 110 16 bit 5 6 5 0 W0PAL 2 0 This bit determin...

Page 568: ... for the active period of the address signal enable to the chip select enable 0 LCD_WR _SETUP 15 12 Numbers of clock cycles for the active period of the CS signal enable to the write signal enable 0 LCD_WR_ACT 11 8 Numbers of clock cycles for the active period of the chip select enable 0 LCD_WR _HOLD 7 4 Numbers of clock cycles for the active period of the chip select disable to the write signal d...

Page 569: ...cription Initial state Reserved 30 7 Not used for normal access Write not zero values to these register make to come out abnormal result 0 RDithPos 6 5 Red Dither bit control 00 5 bit 01 6 bit 10 8 bit 0 GDithPos 4 3 Green Dither bit control 00 5 bit 01 6 bit 10 8 bit 0 BDithPos 2 1 Blue Dither bit control 00 5 bit 01 6 bit 10 8 bit 0 DITHEN_F 0 Dithering Enable bit 0 dithering disable 1 dithering...

Page 570: ...S_CS0 main Signal control 0 Disable High 1 Enable Low 0 SYS_CS1_CON 8 LCD i80 System Interface SYS_CS1 sub Signal control 0 Disable High 1 Enable Low 0 SYS_OE_CON 7 LCD i80 System Interface SYS_OE Signal control 0 Disable High 1 Enable Low 0 SYS_WR_CON 6 LCD i80 System Interface SYS_WR Signal control 0 Disable High 1 Enable Low 0 Reserved 5 2 Reserved Should be set be 0 0 SYS_RS_CON 1 LCD i80 Syst...

Page 571: ...x0000_0000 SIFCCON1 Bit Description Initial State Reserved 23 18 Reserved 0 SYS_WDATA 17 0 LCD i80 System Interface Write Data 0 8 1 28 i80 System Interface Command Control 2 Register Address R Description Reset Value SIFCCON2 0x4C800144 R i80 System Interface Command Data Read register 0x0000_0000 SIFCCON2 Bit Description Initial State Reserved 23 18 Reserved 0 SYS_RDATA 17 0 LCD i80 System Inter...

Page 572: ...ed state ENVID 11b 0 8 1 30 WIN0 Palette RAM Access Address Register Address R W Description Reset Value WIN0_PALENTRY0 0x4C800400 R W Window 0 Palette entry 0 address Undefined WIN0_PALENTRY1 0x4C800404 R W Window 0 Palette entry 1 address Undefined WIN0_PALENTRY255 0x4C8007FC R W Window 0 Palette entry 255 address Undefined 8 1 31 WIN1 Palette RAM Access Address Register Address R W Description ...

Page 573: ...h screen interface can controls input pads XP XM YP and YM to obtain X Y positions on the external touch screen device Touch Screen Interface contains three main blocks these are touch screen pads control logic ADC interface logic and interrupt generation logic 1 1 FEATURES Resolution 10 bit 12 bit controllable Differential Linearity Error 2 0 LSB Integral Linearity Error 4 0 LSB Maximum Conversio...

Page 574: ...screen interface Note that the A D converter device is a recycling type 10 1 MUX PULL_UP XM_SEN YM_SEN XP_SEN YP_SEN Touch screen pads control A D Converter ADC interface Touch screen control ADC input control Interrupt generation SUBINT_ADC SUBINT_TC Waiting for interrupt VDDA_ADC VDDA_ADC AIN9 XP AIN8 XM AIN7 YP AIN6 YM AIN 5 0 VDDA_ADC Figure 22 1 ADC and Touch Screen Interface Block Diagram ...

Page 575: ...UTO_PST 0 XY_PST contorl This mode consists of two states one is X position measurement state and the other is Y position measurement state X position measurement state is operated as the following way set XY_PST is 1 and read out the converted data X position from ADCDAT0 The end of X position conversion can be notified by interrupt INT_ADC Y position measurement state is operated as the followin...

Page 576: ...DCDAT1 register contains the previous converted data 2 2 4 Programming Notes 1 The A D converted data can be accessed by means of interrupt or polling method With interrupt method the overall conversion time from A D converter start to converted data read may be delayed because of the return time of interrupt service routine and data access time With polling method by checking the ADCCON 15 end of...

Page 577: ...aler value Data value 5 255 Note that division factor is N 1 when the prescaler value is N Note ADC frequency should be set less than PCLK by 5 times Ex PCLK 10MHz ADC Frequency 2MHz 0xFF Reserved 5 4 Reserved 0 RESSEL 3 A D converter resolution selection 0 10 bit resolution 1 12 bit resolution 0 STDBM 2 Standby mode select 0 Normal operation mode 1 Standby mode 1 READ_ START 1 A D conversion star...

Page 578: ... enable XM VSSA_ADC 0 XP_SEN 4 XP to VDD Switch Enable 0 Switch enable XP VDDA_ADC 1 Switch disable XP AIN9 Hi z 1 PULL_UP 3 XP Pull up Switch Enable 0 XP pull up enable 1 XP pull up disable 1 AUTO_PST 2 Automatically sequencing conversion of X Position and Y Position 0 Normal ADC conversion 1 Auto measurement of X position Y position 0 XY_PST 1 0 Manually measurement of X Position or Y Position 0...

Page 579: ...tion Initial State DELAY 15 0 Incase of ADC conversion mode Normal Separate Auto conversion ADC conversion is delayed by counting this value Counting clock is PCLK In case of waiting for interrupt mode When stylus down occurs in waiting for interrupt mode counts this value and then generates Interrupt signal INT_TC for filtering noise Counting clock is external input clock X tal or EXTCLK Note Do ...

Page 580: ...nd Y position mirroring AUTO_PST in ADCTSC register 0 Normal ADC conversion 1 Auto measurement of X position Y position XY_PST 13 12 Manual measurement of X position or Y position mirroring XY_PST in ADCTSC register 00 No operation mode 01 X position measurement 10 Y position measurement 11 Waiting for Interrupt Mode XPDATA_12 Normal ADC 11 10 When A D resolution is 12bit X position conversion MSB...

Page 581: ... register 00 No operation mode 01 X position measurement 10 Y position measurement 11 Waiting for Interrupt Mode YPDATA_12 11 10 When A D resolution is 12bit X position conversion MSB 2 bit data value Data value data 11 0 0 0xFFF YPDATA 9 0 Y position conversion data value Data value data 9 0 0 0x3FF 3 6 ADC TOUCH SCREEN UP DOWN INT CHECK REGISTER ADCUPDN Register Address R W Description Reset Val...

Page 582: ...18 R W Analog input channel select 0x0 ADCMUX Bit Description Initial State ADCMUX 3 0 Analog input channel select 0000 AIN 0 0001 AIN 1 0010 AIN 2 0011 AIN 3 0100 AIN 4 0101 AIN 5 0110 AIN 6 YM 0111 AIN 7 YP 1000 AIN8 XM 1001 AIN9 XP 0 NOTE When Touch Screen Pads YM YP XM XP are disabled these ports can be used as Analog input ports AIN6 AIN7 AIN8 AIN9 for ADC ...

Page 583: ...2x16 RXFIFO data structures are included and DMA transfer mode for transmitting or receiving samples can be supported IIS specific clock can be supplied from internal system clock controller through IIS clock divider or direct clock source 2 FEATURE Up to 5 1ch IIS bus for audio interface with DMA based operation Serial 8 16 24 bit per channel data transfers Supports IIS MSB justified and LSB just...

Page 584: ...machine and channel control block as shown in Figure 23 1 Note that each FIFO has 32 bit width and 16 depth structure which contains left right channel data So FIFO access and data transfer are handled with left right pair unit Figure 23 1 shows the internal functional block diagram of IIS interface for actual GPIO pad name please refer prior page s SIGNALS table For more detail guide of GPIO sett...

Page 585: ... be also going out for external IIS codec chip operation If IIS bus interface transmits clock signals to IIS codec IIS bus is master mode But if IIS bus interface receives clock signal from IIS codec IIS bus is slave mode TX RX mode indicates the direction of data flow If IIS bus interface transmits data to IIS codec this is TX mode Conversely IIS bus interface receives data from IIS codec that is...

Page 586: ... FIFO data state Especially FTXEMPT and FRXFULL bit are the ready flag for DMA service request the transmit DMA service request is activated when TXFIFO is not empty and the receiver DMA service request is activated when RXFIFO is not full The DMA transfer uses only handshaking method for single data Note that during DMA acknowledge activation the data read or write operation should be performed D...

Page 587: ...mitting data that is synchronized with the leading edge The LR channel select line indicates the channel being transmitted I2SLRCLK may be changed either on a trailing or leading edge of the serial clock but it does not need to be symmetrical In the slave this signal is latched on the leading edge of the clock signal The I2SLRCLK line changes one clock period before the MSB is transmitted This all...

Page 588: ...ows the audio serial format of IIS MSB justified and LSB justified Note that in this figure the word length is 16 bit and I2SLRCLK makes transition every 24 cycle of I2SSCLK BFS is 48 fs where fs is sampling frequency I2SLRCLK frequency Figure 23 3 IIS Audio Serial Data Formats ...

Page 589: ...0 36 8640 49 1520 NOTE fs represents sampling frequency CODECLK Frequency fs 256 or 384 or 512 or 768 6 5 IIS CLOCK MAPPING TABLE On selecting BFS RFS and BLC bits of I2SMOD register user should refer to the following table Table 23 2 shows the allowable clock frequency mapping relations Table 23 2 IIS Clock Mapping Table RFS Clock Frequency 256 fs 00B 512 fs 01B 384 fs 10B 768 fs 11B 16 fs 10B a ...

Page 590: ...fer Master Slave chapter 2 To configure I2SMOD register and I2SPSR IIS pre scaler register properly 3 To operate system in stability the internal TXFIFO should be almost full before transmission First of all DMA starts because of that reason 4 Basically IIS bus doesn t support the interrupt So you can only check state by polling through accessing SFR 5 If TXFIFO is full now then you make I2SACTIVE...

Page 591: ...he following Ensure the PCLK and CLKAUDIO are coming correctly to the I2S controller and FLUSH the TX FIFO using the TFLUSH bit in the I2SFIC Register I2S FIFO Control Register Please ensure that I2S Controller is configured in one of the following modes TX only mode TX RX simultaneous mode This can be done by programming the TXR bit in the I2SMOD Register I2S Mode Register 1 Then Program the foll...

Page 592: ... the TX FIFO for 8 bits channel or 16 bits channel BLC as shown RIGHT CHANNEL LEFT CHANNEL Figure 23 4 TX FIFO Structure for BLC 00 or BLC 01 LOC 0 LOC 1 LOC 2 LOC 3 LOC 4 LOC 5 LOC 6 LOC 7 LOC 8 LOC 9 LOC 10 LOC 11 LOC 12 LOC 13 LOC 14 LOC 15 0 15 7 BLC 00 BLC 01 16 31 BLC 00 BLC 01 23 ...

Page 593: ...the serial data transmission on the I2SSDO The transmission is stopped once the current Left Right channel is transmitted If the control registers in the I2SCON Register I2S Control Register and I2SMOD Register I2S Mode Register are to be reprogrammed then it is advisable to disable the TX channel If the TX channel is enabled while the FIFO is empty no samples are read from the FIFO The Status of ...

Page 594: ... FIFO Control Register and the I2S controller is configured in any of the modes Receive only Receive Transmit simultaneous mode This can be done by Programming the TXR bit in the I2SMOD Register I2S Mode Register 1 Then Program the following parameters according to the need IMS SDF BFS BLC LRP For Programming the above mentioned fields please refer I2SMOD Register I2S Mode Register 2 Once ensured ...

Page 595: ...the RX FIFO for 8 bits channel or 16 bits channel BLC as shown RIGHT CHANNEL LEFT CHANNEL Figure 23 6 RX FIFO Structure for BLC 00 or BLC 01 LOC 0 LOC 1 LOC 2 LOC 3 LOC 4 LOC 5 LOC 6 LOC 7 LOC 8 LOC 9 LOC 10 LOC 11 LOC 12 LOC 13 LOC 14 LOC 15 0 15 7 BLC 00 BLC 01 16 31 BLC 00 BLC 01 23 ...

Page 596: ...ght channel is received If the control registers in the I2SCON Register I2S Control Register and I2SMOD Register I2S Mode Register are to be reprogrammed then it is advisable to disable the RX channel The Status of RX FIFO can be checked by checking the bits in the I2SFIC Register I2S FIFO Control Register LOC 0 LOC 1 LOC 2 LOC 3 LOC 4 LOC 5 LOC 6 LOC 7 LOC 8 LOC 9 LOC 10 LOC 11 LOC 12 LOC 13 LOC ...

Page 597: ...ce control register 0xC600 IISMOD 0x55000004 R W IIS interface mode register 0x0 IISFIC 0x55000008 R W IIS interface FIFO control register 0x0 IISPSR 0x5500000C R W IIS interface clock divider control register 0x0 IISTXD 0x55000010 W IIS interface transmit data register 0x0 IISRXD 0x55000014 R IIS interface receive data register 0x0 NOTE All registers of IIS interface are accessible by word unit w...

Page 598: ...empty Not Ready to transmit Data FTX1EMPT 14 R TX FIFO1 empty Status Indication 0 TX FIFO1 is not empty Ready to transmit Data 1 TX FIFO1 is empty Not Ready to transmit Data FTX2FULL 13 R TX FIFO2 full Status Indication 0 TX FIFO2 is not full 1 TX FIFO2 is full FTX1FULL 12 R TX FIFO1 full Status Indication 0 TX FIFO1 is not full 1 TX FIFO1 is full LRI 11 R Left Right channel clock indication Note ...

Page 599: ...ated at any time the channel operation will be halted after left right channel data transfer is completed 0 No pause operation 1 Pause operation RXCHPAUSE 3 R W Rx channel operation pause command Note that when this bit is activated at any time the channel operation will be halted after left right channel data transfer is completed 0 No pause operation 1 Pause operation TXDMACTIVE 2 R W Tx DMA act...

Page 600: ...hannel enable 16 SD1 channel enable 15 R W Reserved Program to Zero BLC 14 13 R W Bit Length Control Bit Which decides transmission of 8 16 bits per audio channel 00 16 Bits per channel 01 8 Bits Per Channel 10 24 Bits Per Channel 11 Reserved CDCLKCON 12 R W Determine direction of codec clock I2SCDCLK 0 Supply codec clock to external codec chip from PCLK EPLL EPLLRefCLK 1 Get codec clock from exte...

Page 601: ...hannel and low for right channel SDF 6 5 R W Serial data format 00 IIS format 01 MSB justified left justified format 10 LSB justified right justified format 11 Reserved RFS 4 3 R W IIS root clock codec clock frequency select 00 256 fs where fs is sampling frequency 01 512 fs 10 384 fs 11 768 fs Even in the slave mode this bit should be set for correct BFS 2 1 R W Bit clock frequency select 00 32 f...

Page 602: ... flush command 0 No flush 1 Flush 6 5 R W Reserved Program to zero FRXCNT 4 0 R RX FIFO data count 0 16 NOTE Tx FIFOs Rx FIFO has 32 bit width and 16 depth structure so FIFO data count value ranges from 0 to 16 8 4 IIS PRESCALER CONTROL REGISTER IISPSR Register Address Description Reset Value IISPSR 0x5500000C IIS interface clock divider control register 0x0000_0000 IISPSR Bit R W Description 31 1...

Page 603: ...a is allocated as the following bit fields R 23 0 L 23 0 when 24 bit BLC R 31 16 L 15 0 when 16 bit BLC R 23 16 L 7 0 when 8 bit BLC 8 6 IIS RECEIVE REGISTER IISRXD Register Address Description Reset Value IISRXD 0x55000014 IIS interface receive data register 0x0000_0000 IISRXD Bit R W Description IISRXD 31 0 R RX FIFO read data Note that the left right channel data is allocated as the following b...

Page 604: ...S3C2416X RISC MICROPROCESSOR S3C2416X RISC MICROPROCESSOR 23 22 NOTES ...

Page 605: ... the programming model for the AC97 Controller Unit The information in this chapter requires an understanding of the AC97 revision 2 0 specifications 1 1 FEATURE Independent channels for stereo PCM In Slot3 Slot4 mono MIC In Slot 6 stereo PCM Out Slot3 Slot4 DMA based operation and interrupt based operation All of the channels support only 16 bit samples Variable sampling rate AC97 Codec interface...

Page 606: ...igure 24 1 shows the functional block diagram of S3C2416 AC97 Controller The AC97 signals form the AC link which is a point to point synchronous serial inter connecting that supports full duplex data transfers All digital audio streams and command status information are communicated over the AC link APB I F DMA Engine Interrupt Control MIC in FIFO PCM out FIFO PCM in FIFO SFR AC link I F FSM Contr...

Page 607: ... 16 entries buffer It also has 20 bit I O shift register via AC link Command Addr Register Slot 1 Command Data Register Slot 2 PCM Out Buffer Regfile 16 bit x 2 x 16 Entry Slot 3 Slot4 PWDATA Response Data Register Slot 2 Mic In Buffer RegFile 16 bit x16 Entry Slot 6 PCM In Buffer Regfile 16 bit x 2 x 16 Entry Slot 3 4 PRDATA Input Shift Register 20 bit Output Shift Register 20 bit SDATA_IN SDATA_...

Page 608: ...occurred you must de assert codec ready interrupt Now then you can transmit data from memory to register or from register to memory by using DMA or PIO directly to write data to register If internal FIFOs TX FIFO or RX FIFO is not empty then let data be transmitted In addition you can previously turn on AC Link System reset or Cold reset Set GPIO and Release INTMSK SUBINTMSK bits Enable Codec Read...

Page 609: ...zation for all data transaction on the AC link A data transaction is made up of 256 bits of information broken up into groups of 13 time slots and is called a frame Time slot 0 is called the Tag Phase and is 16 bits long The other 12 time slots are called the Data Phase The Tag Phase contains one bit that identifies a valid frame and 12 bits that identify the time slots in the Data Phase that cont...

Page 610: ...2 of slot 1 are configured to specify the index to the CODEC register Others are filled with 0 s reserved In slot 2 it configured with the data which is for writing because of output frame Slot 2 Command Data Port In slot 2 this is the write data with 16 bit resolution 19 4 is valid data Slot 3 PCM Playback Left channel Slot 3 which is audio output frame is the composite digital audio left stream ...

Page 611: ...A_OUT tag bits at the beginning of each audio output frame to determine which SLOTREQ bits to set active low SLOTREQ bits asserted during the current audio input frame indicate which output slots require data from the controller in the next audio output frame For fixed 48 kHz operation the SLOTREQ bits are set active low and a sample is transferred each frame For multiple sample rate input the tag...

Page 612: ...ng non valid bit positions in the slot with zeroes Slot 6 Microphone Record Data The AC97 Controller only supports 16 bit resolution for the MIC in channel SDATA_OUT BIT_CLK SYNC AC 97 samples SYNC assertion here AC 97 Controller samples first SDATA_IN bit of frame here END of previous Audio Frame Codec Ready Slot 1 Slot 2 Slot 12 0 0 0 19 0 Tag Phase Data Phase 19 0 START of Data phase Slot 1 END...

Page 613: ...bit PR4 data 0x1000 and it does not require the Codec to process other data when it receives a power down request When the Codec processes the request it immediately transitions BITCLK and SDATA_IN to a logic low level The AC97 Controller drives SYNC and SDATA_OUT to a logic low level after programming the AC_GLBCTRL register 5 1 2 Waking up the AC link Wake Up Triggered by the AC97 Controller AC ...

Page 614: ... to their default power on reset values nRESET is an asynchronous AC97 input 6 1 2 Warm AC97 Reset A Warm AC97 reset reactivates the AC link without altering the current AC97 register values A warm reset is generated when BITCLK is absent and SYNC is driven high In normal audio frames SYNC is a synchronous AC97 input When BITCLK is absent SYNC is treated as an asynchronous input used to generate a...

Page 615: ...ng 1 CODEC_READY TRANS_DATA POWER_DOWN WARM_RESET ACLINK_ON 5 CODEC_WAKEUP 5 4 3 6 8 7 6 7 8 2 3 4 9 9 9 9 9 9 COLD_RESET PRESETn Figure 24 9 AC97 State Diagram This is the state diagram of AC97 controller It is helpful to understand AC97 controller state machine State above figure is synchronized by peripheral clock PCLK It is able to monitor state at AC_GLBSTAT register ...

Page 616: ...bal Status Register 0x00000001 AC_CODEC_CMD 0x5B000008 R W AC97 Codec Command Register 0x00000000 AC_CODEC_STAT 0x5B00000C R AC97 Codec Status Register 0x00000000 AC_PCMADDR 0x5B000010 R AC97 PCM Out In Channel FIFO Address Register 0x00000000 AC_MICADDR 0x5B000014 R AC97 MIC In Channel FIFO Address Register 0x00000000 AC_PCMDATA 0x5B000018 R W AC97 PCM Out In Channel FIFO Data Register 0x00000000...

Page 617: ...nable FIFO is half empty 0 PCM in channel threshold interrupt enable 17 0 Disable 1 Enable FIFO is half full 0 MIC in channel threshold interrupt enable 16 0 Disable 1 Enable FIFO is half full 0 15 14 Reserved 00 PCM out channel transfer mode 13 12 00 Off 01 PIO 10 DMA 11 Reserved 00 PCM in channel transfer mode 11 10 00 Off 01 PIO 10 DMA 11 Reserved 00 MIC in channel transfer mode 9 8 00 Off 01 P...

Page 618: ...hreshold interrupt 17 0 Not requested 1 Requested 0 MIC in channel threshold interrupt 16 0 Not requested 1 Requested 0 15 3 Reserved 0x000 Controller main state 2 0 000 Idle 001 Init 010 Ready 011 Active 100 LP 101 Warm 001 8 4 AC97 CODEC COMMAND REGISTER AC_CODEC_CMD When you control writing or reading you must set the Read enable bit If you want to write data to the AC97 Codec you set the index...

Page 619: ...steps 1 Write command address and data on the AC_CODEC_CMD register with Bit 23 1 2 Have a delay time 3 Read command address and data from AC_CODEC_STAT register 8 6 AC97 PCM OUT IN CHANNEL FIFO ADDRESS REGISTER AC_PCMADDR To index the internal PCM FIFOs address Register Address R W Description Reset Value AC_PCMADDR 0x5B000010 R AC97 PCM Out In Channel FIFO Address Register 0x00000000 AC_PCMADDR ...

Page 620: ... channel FIFO data register Register Address R W Description Reset Value AC_PCMDATA 0x5B000018 R W AC97 PCM Out In Channel FIFO Data Register 0x00000000 AC_PCMDATA Bit Description Initial State Right data 31 16 PCM out in right channel FIFO data Read PCM in right channel Write PCM out right channel 0x0000 Left data 15 0 PCM out in left channel FIFO data Read PCM in left channel Write PCM out left ...

Page 621: ...ster mode only this block always sources the main serial clock The sources of PCM clock are based on an internal PCLK or an External Clock Input 16bit 32depth and output 16bit 32depth FIFOs to buffer data DMA interface for Tx and or Rx 1 2 SIGNALS Name Direction Description PCM_SCLK Output Serial shift clock PCM_FSYNC Output Serial data indicator and synchronizer PCM_SDI Output Serial PCM input da...

Page 622: ...The TX FIFO provides the 16 bit data word to be serially shifted out This data is serially shifted out MSB first one bit per PCMSCLK The PCM serial output data PCMSOUT is clocked out using the rising edge of the PCMSCLK The MSB bit position relative to the PCMFSYNC is programmable to be either coincident with the PCMFSYNC or one PCMSCLK later After all 16 bits have been shifted out an interrupt ca...

Page 623: ...SB_POS bits in PCMCTL register to be 1 PCMFSYNC PCMSOUT 15 14 1 0 dont care 15 output output output PCMSCLK input pcm_irq sync to DSP clk 15 14 1 0 dont care 15 input internal PCMSIN PCMSOURCE_CLK datain_reg_valid Figure 25 2 PCM timing TX_MSB_POS RX_MSB_POS 1 NOTE In all cases the PCM shift timing is derived by dividing the input clock PCMSOURCE_CLK While the timing is based upon the PCMSOURCE_CL...

Page 624: ...CTL_SERCLK_SEL PCM PCM_CDCLK Clock Divider PCM SOURCE_ CLK PCM_SCLK PCM_FSYNC 1 SYNC_DIV 1 1 16 1 512 1 2 1 1024 even number Figure 25 3 Input Clock Diagram for PCM S3C2416 PCM is able to select clock either PCLK or External Clock Refer figure 25 3 To enable clock gating please refer to the SYSCON part SCLKCON PCLKCON ...

Page 625: ... W PCM Main Control 0x00000000 PCM_CLKCTL 0x5C000004 R W PCM Clock and Shift control 0x00000000 PCM_TXFIFO 0x5C000008 R W PCM TxFIFO write port 0x00010000 PCM_RXFIFO 0x5C00000C R W PCM RxFIFO read port 0x00010000 PCM_IRQ_CTL 0x5C000010 R W PCM Interrupt Control 0x00000000 PCM_IRQ_STAT 0x5C000014 R PCM Interrupt Status 0x00000000 PCM_FIFO_STAT 0x5C000018 R PCM FIFO Status 0x00000000 PCM_CLRINT 0x5C...

Page 626: ...DMA uses TXFIFO_ALMOST_FULL as the DMA request keep requesting data until the FIFO is almost full In some circumstances the DMA write one more word after the DMA_req goes away Thus the almost_full flag most go active with at least space for one extra word in the fifo 0 RXFIFO_DIPSTICK 12 7 Determines when the almost_full almost_empty flags go active for the RXFIFO RXFIFO_ALMOST_EMPTY fifo_depth fi...

Page 627: ...on the falling edge of PCMSCLK during the cycle after the PCMFSYNC is high 0 PCM_TXFIFO_EN 2 Enable the TXFIFO note 1 0 PCM_RXFIFO_EN 1 Enable the RXFIFO note 1 0 PCM_PCM_ENABL E 0 PCM enable signal 1 Enables the serial shift state machines note 2 The enable must be set HIGH for the PCM to operate 0 The PCMSOUT will not toggle The internal divider counters serial shift register s counter are held ...

Page 628: ...K and PCMFSYNC is operated 1 0 CTL_SERCLK_SEL 18 Select the source of the PCMSOURCE_CLK 0 External clock 1 PCLK 0 SCLK_DIV 17 9 Controls the divider used to create the PCMSCLK based on the PCMSOURCE_CLK 1 2 1 1024 PCMSLCK will be PCMSOURCE_CLK 2 SCLK_DIV 1 000 SYNC_DIV 8 0 Controls the frequency of the PCMFSYNC signal based on the PCMSCLK 1 1 1 512 Freq of PCMFSYNC Freq of PCMSCLK SYNC_DIV 1 000 N...

Page 629: ... definitions for the PCM_TXFIFO Register are shown below PCM_TXFIFO Bit Description Initial State Reserved 31 17 Reserved TXFIFO_DVALID 16 TXFIFO data is valid Write don t care Read TXFIFO read data valid 1 Valid 0 Invalid probably read an empty fifo 1 TXFIFO_DATA 15 0 Write Write PCM data to TXFIFO Note The TXFIFO is read by the PCM serial shift engine Read Read PCM data from TXFIFO for supportin...

Page 630: ... definitions for the PCM_RXFIFO Register are shown below PCM_RXFIFO Bit Description Initial State Reserved 31 17 Reserved RXFIFO_DVALID 16 RXFIFO data is valid Write don t care Read TXFIFO read data valid 1 Valid 0 Invalid probably read an empty fifo 1 RXFIFO_DATA 15 0 Write Write PCM data to RXFIFO for debugging RXFIFO Read Read PCM data from RXFIFO Note The RXFIFO is written by the PCM serial sh...

Page 631: ...to the ARM subsystem 0 Reserved 13 Reserved 0 TRANSFER_DONE 12 Interrupt is generated every time the serial shift for a 16bit PCM Data word completes 1 IRQ source enabled 0 IRQ source disabled 0 TXFIFO_EMPTY 11 Interrupt is generated whenever the TxFIFO is empty 1 IRQ source enabled 0 IRQ source disabled 0 TXFIFO_ALMOST_ EMPTY 10 Interrupt is generated whenever the TxFIFO is ALMOST_EMPTY which is ...

Page 632: ...terrupt is generated whenever the RxFIFO is empty 1 IRQ source enabled 0 IRQ source disabled 0 RXFIFO_ALMOST_ EMPTY 4 Interrupt is generated whenever the RxFIFO is ALMOST_EMPTY which is defined as RX_FIFO_DEPTH RX_FIFO_DIPSTICK 1 IRQ source enabled 0 IRQ source disabled 0 RX_FIFO_FULL 3 Interrupt is generated whenever the RxFIFO is full 1 IRQ source enabled 0 IRQ source disabled 0 RX_FIFO_ALMOST_ ...

Page 633: ...Description Initial State RXFIFO_ERROR_ OVERFLOW 0 Interrupt is generated for RxFIFO overflow ERROR This occurs whenever the RxFIFO is written when it is already full This is considered an ERROR and will have unexpected results 1 IRQ source enabled 0 IRQ source disabled 0 ...

Page 634: ... occurred 0 IRQ is not occurred 0 TXFIFO_ALMOST _EMPTY 10 Interrupt is generated whenever the TxFIFO is ALMOST empty 1 IRQ is occurred 0 IRQ is not occurred 0 TXFIFO_FULL 9 Interrupt is generated whenever the TX FIFO is full 1 IRQ is occurred 0 IRQ is not occurred 0 TXFIFO_ALMOST _FULL 8 Interrupt is generated whenever the TX FIFO is ALMOST full 1 IRQ is occurred 0 IRQ is not occurred 0 TXFIFO_ERR...

Page 635: ...t occurred 0 RXFIFO_ERROR _STARVE 1 Interrupt is generated for RX FIFO starve ERROR This occurs whenever the RX FIFO is read when it is still empty This is considered as an ERROR and will have unexpected results 1 IRQ is occurred 0 IRQ is not occurred 0 RXFIFO_ERROR _OVERFLOW 0 Interrupt is generated for RX FIFO overflow ERROR This occurs whenever the RX FIFO is written when it is already full Thi...

Page 636: ...X FIFO data count 0 32 0 TXFIFO_EMPTY 13 1 TXFIFO is empty 0 TXFIFO is not empty 0 TXFIFO_ALMOST_EMPTY 12 1 TXFIFO is ALMOST_EMPTY 0 TXFIFO is not ALMOST_EMPTY 0 TXFIFO_FULL 11 1 TXFIFO is full 0 TXFIFO is not full 0 TXFIFO_ALMOST_FULL 10 1 TXFIFO is ALMOST_FULL 0 TXFIFO is not ALMOST_FULL 0 RXFIFO_COUNT 9 4 RX FIFO data count 0 32 RXFIFO_EMPTY 3 1 RXFIFO is empty 0 RXFIFO is not empty 0 RXFIFO_AL...

Page 637: ...interrupts for ARM Reading this register is not allowed Clearing interrupt must be prior to resolving the interrupt condition otherwise another interrupt that would occur after this interrupt may be ignored Register Address R W Description Reset Value PCM_CLRINT 0x5C000020 W PCM INTERRUPT CLEAR The bit definitions for the PCM_CLRINT Register are shown below PCM_CLRINT Bit Description Initial State...

Page 638: ...PCM AUDIO INTERFACE S3C2416X RISC MICROPROCESSOR 25 18 NOTES ...

Page 639: ...er Symbol Min Max Unit VDDi VDDiarm VDDalive VDDA_MPLL VDDA_EPLL VDDI_UDEV 0 5 1 8 VDD_OP1 VDD_OP2 VDD_OP3 VDD_RTC VDD_SRAM VDD_SD VDDA_ADC VDDA33x VDD_USBOSC 0 5 4 6 DC Supply Voltage VDD_SDRAM 0 5 3 6 DC Input Voltage VIN 0 5 3 6 4 8 DC Output Voltage VOUT 0 5 3 6 4 8 V DC Input Current II O 200 mA Storage Temperature TSTG 65 to 150 ο C ...

Page 640: ...tage for USBOSC PAD VDD_USBOSC 1 7 1 8 2 5 3 3 3 6 DC Supply Voltage for SRAM I F VDD_SRAM 1 7 1 8 2 5 3 3 3 6 DC Supply Voltage for SDRAM I F VDD_SDRAM 1 7 1 8 2 5 2 7 DC Supply Voltage for RTC VDD_RTC 1 7 1 8 2 5 3 3 3 6 VDD_SD 1 7 1 8 2 5 3 3 3 6 DC Supply Voltage for SD LCD VDD_LCD 1 7 1 8 2 5 3 3 3 6 DC Supply Voltage for USB PHY 3 3V VDDA33x 3 3 5 3 3 3 3 5 DC Supply Voltage for USB PHY 1 2V...

Page 641: ...B OSC PAD VDD_USBOSC 1 7 1 8 2 5 3 3 3 6 DC Supply Voltage for SRAM I F VDD_SRAM 1 7 1 8 2 5 3 3 3 6 DC Supply Voltage for SDRAM I F VDD_SDRAM 1 7 1 8 2 5 2 7 DC Supply Voltage for RTC VDD_RTC 1 7 1 8 2 5 3 3 3 6 VDD_SD 1 7 1 8 2 5 3 3 3 6 DC Supply Voltage for SD LCD VDD_LCD 1 7 1 8 2 5 3 3 3 6 DC Supply Voltage for USB PHY 3 3V VDDA33x 3 3 5 3 3 3 3 5 DC Supply Voltage for USB PHY 1 2V VDDI_UDEV...

Page 642: ...wn Vin VDD VDD 1 8V 5 20 40 uA Vin 5V VDD 3 3V 10 30 60 Vin 3 3V VDD 2 5V 6 16 50 Iih Tolerant Input Buffer with pull up Vin 3 3V VDD 1 8V 2 8 18 uA Low Level Input Current Input Buffer Vin VSS 10 10 uA VDD 3 3V 130 70 20 VDD 2 5V 80 40 10 Iil Input Buffer with pull up Vin VSS VDD 1 8V 40 20 5 uA Voh Type A B C Ioh 100uA VDD 0 2 V Vol Type A B C Iol 100uA 0 2 V Ioz Tri State Output Leakage Current...

Page 643: ...n VDD VDD 1 8V 5 20 40 uA Vin 3 3V VDD 2 5V 3 10 40 Iih Tolerant Input Buffer with pull up Vin 3 3V VDD 1 8V 1 4 10 uA Low Level Input Current Input Buffer Vin VSS 10 10 uA VDD 2 5V 80 40 10 Iil Input Buffer with pull up Vin VSS VDD 1 8V 40 20 5 uA Voh Type A B C Ioh 100uA VDD 0 2 V Vol Type A B C Iol 100uA 0 2 V Ioz Tri State Output Leakage Current Vout VSS or VDD 10 10 uA CIN Input capacitance A...

Page 644: ...age RL 15KΩ to GND 2 8 3 6 V ILZ Tri state leakage current 10 10 uA Cin Transceiver capacitance Pin to GND 10 pF RPD Pull down resistance on pins DP DM Enable internal resistors 10 20 kΩ RPU Pull up resistance on DP Enable internal resistor 1 2 kΩ ZDRV Driver output impedance Steady state drive 1 39 44 Ω ZINP Input impedance 10 MΩ VTERM Termination voltage for upstream port pull up 3 0 3 6 V Table...

Page 645: ...YC NOTE The clock input from the XTIpll pin Figure 26 1 XTIpll Clock Timing tEXTHIGH 1 2 VDD_OP1 VIL VIL VIH VIH 1 2 VDD_OP1 tEXTLOW tEXTCYC NOTE The clock input from the EXTCLK pin Figure 26 2 EXTCLK Clock Input Timing HCLK internal EXTCLK tEX2HC Figure 26 3 EXTCLK HCLK in case that EXTCLK is used without the PLL ...

Page 646: ...ELECTRICAL DATA S3C2416X RISC MICROPROCESSOR 26 8 HCLK internal SCLK CLKOUT HCLK tHC2CK tHC2SCLK Figure 26 4 HCLK CLKOUT SCLK in case that EXTCLK is used Figure 26 5 Manual Reset Input Timing ...

Page 647: ...K VCO output MCU operates by XTIpll or EXTCLK clcok Clock Disable tPLL FCLK is new frequency Power PLL can operate after OM 3 2 is latched PLL is configured by S W first time VCO is adapted to new clock frequency FCLK tRST2RUN Figure 26 6 Power On Oscillation Setting Timing ...

Page 648: ...416X RISC MICROPROCESSOR 26 10 XTIpll VCO Output Clock Disable FCLK Several slow clocks XTIpll or EXTCLK Sleep mode is initiated tOSC2 EXTCLK Wake up from sleep mode Figure 26 7 Sleep Mode Return Oscillation Setting Timing ...

Page 649: ...S3C2416X RISC MICROPROCESSOR ELECTRICAL DATA 26 11 Figure 26 8 SMC Synchronous Read Timing Figure 26 9 SMC Asynchronous Read Timing ...

Page 650: ...CAL DATA S3C2416X RISC MICROPROCESSOR 26 12 tCSD_A tADDRD_A tWED tDOD_A Asynchronous Write SMCLK RADDR RDATA nRCS nRWE A D A Figure 26 10 SMC Asynchronous Write Timing Figure 26 11 SMC Synchronous Write Timing ...

Page 651: ...S3C2416X RISC MICROPROCESSOR ELECTRICAL DATA 26 13 RADDR 26 0 RDATA 31 0 nRCS nROE nW AIT A D A SMCLK tW S tHS Figure 26 12 SMC Wait Timing ...

Page 652: ...LED tWED tWED tWDD tWDD tALED tWED tALED tWED tWDD TACLS tWDD TWRPH0 TWRPH1 ADDRESS tWDD tALED tWED tALED tWED tWDD TACLS Nand booting After Nand booting HCLK nFWE TWRPH0 TWRPH1 HCLK nFRE TWRPH0 TWRPH1 RDATA tWED tWED tWDD tRED tRED tRDS tRDH tWDD WDATA RDATA 15 0 HCLK FALE nFWE RDATA 15 0 HCLK FALE nFWE Figure 26 13 Nand Flash Timing ...

Page 653: ...S3C2416X RISC MICROPROCESSOR ELECTRICAL DATA 26 15 Figure 26 14 SDRAM READ WRITE Timing Trp 2 Trcd 2 Tcl 2 DW 16 bit ...

Page 654: ...E tSWD tDQSQ nSCAS READ TIMING RL 3 nSWE tSCD Figure 26 15 DDR2 Timing Parameter Symbol Min Max Unit DDR2 First DQS latching transition to associated clock edge tDQSS 0 4 0 66 ns DDR2 DQ and DM output setup time tDS x 2 70 ns DDR2 DQ and DM output hold time tDH x 1 53 ns DDR2 DQS DQ skew for DQS and associated DQ signals tDQSQ x 0 7 ns ...

Page 655: ...S3C2416X RISC MICROPROCESSOR ELECTRICAL DATA 26 17 SCLK nSRAS tSAD nSCAS SDATA SADDR DQMx tSRD SCKE A10 AP nSCSx tSCSD nSWE tSAD tSCD tSWD 1 tSAD tSCSD tSRD HZ 1 tSWD Figure 26 16 SDRAM MRS Timing ...

Page 656: ... SCLK nSRAS tSAD Trp nSCAS SDATA SADDR DQMx tSRD SCKE A10 AP nSCSx tSCSD nSWE tSAD tSCD tSWD 1 tSAD tSCSD tSRD 1 1 HZ Trc NOTE Before executing auto self refresh command all banks must be in idle state Figure 26 17 SDRAM Auto Refresh Timing Trp 2 Trc 4 ...

Page 657: ... tCADH tXAD nXDREQ nXDACK Read Write Min 3SCLK Figure 26 18 External DMA Timing Handshake Single transfer VSYNC HSYNC VDEN Tf2hsetup Tf2hhold Tvspw Tvbpd Tvfpd HSYNC VCLK VD VDEN Tl2csetup Tvclkh Tvclk Tvclkl Tvdhold Tvdsetup Tve2hold Figure 26 19 TFT LCD Controller Timing ...

Page 658: ...O Output TLRId TDS TDH Figure 26 20 IIS Interface Timing I2S Master Mode Only I2SLRCLK Input I2SSCLK Input I2SSDI Input TLRId TDS TDH Figure 26 21 IIS Interface Timing I2S Slave Mode Only tSTOPH tSTARTS tSDAS tSDAH tBUF tSCLHIGH tSCLLOW fSCL IICSCL IICSDA Figure 26 22 IIC Interface Timing ...

Page 659: ...CS tHSDDD SD_CMD in tHSDDH tHSDDS SD_DAT out SD_DAT in Figure 26 23 High Speed SDMMC Interface Timing SPICLK tSPIMIH tSPIMIS XspiMOSI MO XspiMOSI SI XspiMISO MI tSPIMOD tSPISIS tSPISIH XspiMISO SO tSPISOD XspiCS tSPICSSS tSPICSSD Figure 26 24 High Speed SPI Interface Timing CPHA 0 CPOL 1 ...

Page 660: ...ELECTRICAL DATA S3C2416X RISC MICROPROCESSOR 26 22 VCRS Differential Data Lines TR TF 90 10 90 10 Rise Time Fall Time Figure 26 25 USB Timing Data signal rise fall time Figure 26 26 PCM Interface Timing ...

Page 661: ...clock input high level pulse width tEXTHIGH 3 5 ns External clock to HCLK without PLL tEX2HC 5 13 ns HCLK internal to CLKOUT tHC2CK 3 3 8 8 ns HCLK internal to SCLK tHC2SCLK 1 9 5 8 ns Reset assert time after clock stabilization tRESW 4 XTIpll or EXTCLK PLL Lock Time tPLL 300 us Sleep mode return oscillation setting time note 2 tOSC2 2 524290 XTIpll or EXTCLK The interval before CPU runs after nRE...

Page 662: ...MC Address Delay tADDRD 2 3 6 49 ns SMC Data Output Delay tDOD 2 8 6 53 ns SMC nWAIT setup time tWS 2 3 5 ns SMC nWAIT hold time tWH 0 0 ns Table 26 10 NFCON Bus Timing Constants VDDi 1 3V 0 05V 400MHz VDDi 1 3 V 0 05V 266MHz TA 40 to 85 C VDD_SRAM 1 8V 0 1V Parameter Symbol Min Max Unit NFCON Chip Enable delay tCED 10 35 ns NFCON CLE delay tCLED 9 86 ns NFCON ALE delay tALED 9 73 ns NFCON Write E...

Page 663: ... 84 ns SDRAM Row active Delay tSRD 1 70 3 86 ns SDRAM Column active Delay tSCD 1 68 3 93 ns SDRAM Byte Enable Delay tSBED 1 63 4 31 ns SDRAM Write enable Delay tSWD 1 63 3 74 ns SDRAM read Data Setup time tSDS 1 50 ns SDRAM read Data Hold time tSDH 1 50 ns SDRAM output Data Delay tSDD 1 57 4 61 ns SDRAM Clock Enable Delay tCKED 1 69 4 02 ns NOTE If CL increases over the 15pF operation conditions f...

Page 664: ...LK pulse width low Tvclkl 0 3 Pvclk Vertical sync pulse width Tvspw VSPW 1 Phclk note2 Vertical back porch delay Tvbpd VBPD 1 Phclk Vertical front porch delay Tvfpd VFPD 1 Phclk Hsync setup to VCLK falling edge Tl2csetup 0 3 Pvclk VDEN set up to VCLK falling edge Tde2csetup 0 3 Pvclk VDEN hold from VCLK falling edge Tde2chold 0 3 Pvclk VD setup to VCLK falling edge Tvd2csetup 0 3 Pvclk VD hold fro...

Page 665: ... fSCL std 100 fast 400 kHz SCL high level pulse width tSCLHIGH std 4 0 fast 0 6 μs SCL low level pulse width tSCLLOW std 4 7 fast 1 3 μs Bus free time between STOP and START tBUF std 4 7 fast 1 3 μs START hold time tSTARTS std 4 0 fast 0 6 μs SDA hold time tSDAH std 0 fast 0 std fast 0 9 μs SDA setup time tSDAS std 250 fast 100 ns STOP setup time tSTOPH std 4 0 fast 0 6 μs NOTES Std means Standard...

Page 666: ... ns Feedback Delay 0nS 4 ns Feedback Delay 2nS 3 ns Feedback Delay 4nS 2 ns SPI MISO Master Input Setup time Feedback Delay 6nS tSPIMIS 1 ns Feedback Delay 0nS 4 ns Feedback Delay 2nS 6 ns Feedback Delay 4nS 9 ns SPI MISO Master Input Hold time Feedback Delay 6nS tSPIMIH 11 ns SPI MISO Slave output Delay time tSPISOD 10 ns SPI MOSI Slave Input Setup time tSPISIS 4 ns SPI MOSI Slave Input Hold time...

Page 667: ...00 µA Suspended Current Hot Temp 8 C 3 mA Input Levels for Full speed Differential Input Sensitivity VDI 0 2 V Differential Common Mode Range VCM 0 8 2 5 Input Levels for High speed Differential Common Mode Range VHSCM 50 500 mV HS Squelch detection threshold VHSSQ 100 200 mV Output Levels for FS Low VOL 0 0 0 3 V High VOH 2 8 3 6 V Output Levels for HS HS data signaling high VHSOH 360 460 mV HS d...

Page 668: ...r Electrical Characteristics VDDi 1 3V 0 05V 400MHz VDDi 1 3 V 0 05V 266MHz TA 40 to 85 C VDDA33x 3 3V 0 3V Parameter Symbol Condition Min Max Unit Driver Characteristics Transition Time Rising Time Falling Time TR TF 500 500 ps ps Drive Output Resistance ZDRV Steady state drive 40 5 49 5 ohm Table 26 21 High Speed SDMMC Interface Transmit Receive Timing Constants VDDi 1 3V 0 05V 400MHz VDDi 1 3 V...

Page 669: ...C VDD 3 3V 0 3V 2 5V 0 2V 1 8V 0 1V Parameter Symbol Min Typ Max Unit PCMSCLK clock width 1 tCW 0 128 8 192 MHz PCMSCLK to PCMFSYNC delay tdFSYNC 0 5 ns PCMSCLK to PCMSOUT delay tdSOUT 0 5 ns PCMSIN setup time tsetupSIN 15 ns PCMSIN hold time tholdSIN 10 ns NOTE This table is applied to PCM0 and PCM1 respectively ...

Page 670: ...ELECTRICAL DATA S3C2416X RISC MICROPROCESSOR 26 32 NOTES ...

Page 671: ...S3C2416X RISC MICROPROCESSOR MECHANICAL DATA 30 1 27 MECHANICAL DATA 1 PACKAGE DIMENSIONS Figure 27 1 330 FBGA 1414 Package Dimension 1 Top View ...

Page 672: ...MECHANICAL DATA S3C2416X RISC MICROPROCESSOR 30 2 Figure 27 2 330 FBGA 1414 Package Dimension 2 Bottom View ...

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