UART
S3C2416X RISC MICROPROCESSOR
14-2
2 BLOCK
DIAGRAM
Buad-rate
Generator
Control
Unit
Transmitter
Receiver
Peripheral BUS
TXDn
Clock Source
(PCLK, EXTUARTCLK, EPLL clock/n)
RXDn
Transmit FIFO Register
(FIFO mode)
Transmit Holding Register
(Non-FIFO mode)
Receive FIFO Register
(FIFO mode)
Receive Holding Register
(Non-FIFO mode only)
In FIFO mode, all 64 Byte of Buffer register are used as FIFO register.
In non-FIFO mode, only 1 Byte of Buffer register is used as Holding register.
Transmit Shifter
Transmit Buffer
Register(64 Byte)
Receive Shifter
Receive Buffer
Register(64 Byte)
Figure 14-1. UART Block Diagram (with FIFO)
Summary of Contents for S3C2416
Page 122: ...BUS MATRIX EBI S3C2416X RISC MICROPROCESSOR 3 4 NOTES ...
Page 204: ...DMA CONTROLLER S3C2416X RISC MICROPROCESSOR 8 18 NOTES ...
Page 284: ...WATCHDOG TIMER S3C2416X RISC MICROPROCESSOR 11 6 NOTES ...
Page 320: ...REAL TIME CLOCK S3C2416X RISC MICROPROCESSOR 13 16 NOTES ...
Page 344: ...UART S3C2416X RISC MICROPROCESSOR 14 24 NOTES ...
Page 380: ...USB2 0 DEVICE S3C2416X RISC MICROPROCESSOR 16 34 NOTES ...
Page 432: ...2D S3C2416X RISC MICROPROCESSOR 18 38 NOTES ...
Page 446: ...HS_SPI CONTROLLER S3C2416X RISC MICROPROCESSOR 19 14 NOTES ...
Page 604: ...S3C2416X RISC MICROPROCESSOR S3C2416X RISC MICROPROCESSOR 23 22 NOTES ...
Page 638: ...PCM AUDIO INTERFACE S3C2416X RISC MICROPROCESSOR 25 18 NOTES ...
Page 670: ...ELECTRICAL DATA S3C2416X RISC MICROPROCESSOR 26 32 NOTES ...