2-7
2
MAIN BOARD_Circuit Diagram 3/9
HEAD_UD
/WWE
0
/RRD2
/RESET1
/I
NT
DDA
/F0_INTRE
Q
/I
NT
USB_0
/IRL
0
/IRL
1
/IRL
2
/IRL
3
/PA
NEL
/SW0
/SW1
/SW2
/LED
/L
CD
_CS
LC
D_
E
LC
D_
R
S
/AD_CS
AD_CK
AD_IN
AD_OUT
CROP
_
ON
P
INCHP
OS
DB[
0
..
31]
LC
D_
R
W
RTC_CE
RTC_CL
K
RTC_W
DATA
/SEN
SO
R
/SERIA
L_ST
AR
T
/SRVBRD_RESET
/MTRERR
VCC3
RTC_DATA
MA[
0
..
25]
MA22
MA23
MA24
MA25
5
5
4
4
6
6
3
3
7
7
2
2
8
8
1
1
RA79
E
X
BV8V103J
C27
100p
R136
150
C28
100p
R156
150
/P
S_SENS
DB[
0
..
31]
MA[
0
..
25]
P
C
271
CE
0.
1u
P
C
278
CE
0.
1u
P
C
277
CE
0.
1u
VCC3
P
C
270
CE
0.
1u
VCC3
VCC3
VCC3
P
C
111
CE
0.
1u
VCC3
P
C
272
CE
0.
1u
P
C
276
CE
0.
1u
P
C
279
CE
0.
1u
VCC3
P
C
109
CE
0.
1u
VCC3
VCC3
VCC3
P
C
267
CE
0.
1u
P
C
264
CE0.
1u(NON)
P
C
275
CE
0.
1u
P
C
268
CE
0.
1u
PC
9
4
CE
0.
1u
P
C
262
CE
0.
1u
P
C
261
CE
0.
1u
VCC3
PC
9
5
CE
0.
1u
VCC3
VCC3
VCC3
P
C
260
CE
0.
1u
VCC3
PC
9
9
CE
0.
1u
P
C
114
CE
0.
1u
P
C
115
CE
0.
1u
VCC3
PC
9
8
CE
0.
1u
VCC3
VCC3
VCC3
P
C
266
CE
0.
1u
VCC3
PC
9
3
CE
0.
1u
VCC3
/F
IFO_HALF_NE
T
PR_TXD
PR_RXD
PR_RTS
PR_CTS
/F
IFO_HALF_NE
T
PR_TXD
PR_RXD
PR_RTS
PR_CTS
/PRN
_RST
/PRN
_RST
/WR_FU
LL
/WR_ST
B
/RBE0
/RBE1
/RBE2
/RBE3
/WR_FU
LL
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB8
DB9
DB10
DB11
DB12
DB13
DB14
DB15
DB16
DB17
DB18
DB19
DB20
DB21
DB22
DB23
DB24
DB25
DB26
DB27
DB28
DB29
DB30
DB31
MA19
MA20
MA21
nCS
1
DAT
A
2
Vc
c
3
GND
4
ASDI
5
DCLK
6
Vc
c
7
Vc
c
8
IC206
EP
C
S
1
VCC3
VCC3
VCC3
CONF_DONE
CONF_DONE
VCC3
1
2
3
4
5
6
7
8
9
10
CN16
53398-1090
DCLK
CONF_DONE
VCC3
nCONFIG
CONF_DONE
nCONFIG
nCONFIG
nCONFIG
nCE
nCE
DCLK
DCLK
DCLK
DATA
0
DATA0
DAT
A0
DAT
A0
nCS
nCS
nCE
nCE
nCS
nCS
ASDO
ASDO
ASDO
VCC3
T88
VCC3
VCC1.
2
VCC3
VCC3
VCC3
VCC1.
2
CL
K
60_1
R134
33
CL
K
60_1
EXD0
EXD1
EXD2
EXD3
EXD4
EXD5
EXD6
EXD7
EXD8
EXD9
EXD10
EXD11
EXD12
EXD13
EXD14
EXD15
EXD16
EXD17
EXD18
EXD19
EXD20
EXD21
EXD22
EXD23
EXD24
EXD25
EXD26
EXD27
EXD28
EXD29
EXD30
EXD31
E
XD[
0.
.31]
E
XD[
0.
.31]
/WR_ST
B
/RBE0
/RBE1
/RBE2
/RBE3
VCC3
/RESET1
/CCS0
/CS
4
/CS
6
/A
LT
_
R
ESET
/A
LT
_CONF_DONE
/A
LT
_CONFIG
/A
LT
_DAT
A
/A
L
T
_D
CL
K
/A
L
T
_S
TA
TU
S
OE
1
OUT
3
VCC
4
GND
2
Y4
SG-710E
CK
14.
7456MHz
R132
33
VCC3
VCC3
T152
T99
VCC3
/CS
4
/CS
6
/WWE
0
/RRD2
/LED
/SW0
/SW1
/SW2
/PA
NEL
/SEN
SO
R
/MTRERR
/SERIA
L_ST
AR
T
/SRVBRD_RESET
/P
S_SENS
CROP
_
ON
/USBCS
/GAT
E1
/GAT
E2
T
T
XD3
RRXD3
/GAT
E1
/GAT
E2
/U
S
B
CS
T
T
XD3
RRXD3
/L
CD
_CS
LC
D_
E
LC
D_
R
S
LC
D_
R
W
RT
C_DAT
A
RT
C_W
DAT
A
RTC_CL
K
RTC_CE
AD_IN
/AD_CS
AD_CK
AD_OUT
/IRL
0
/IRL
1
/IRL
2
/IRL
3
/I
NT
USB_0
MA18
/I
NT
DDA
/F0_INTRE
Q
/A
L
T
_S
TA
TU
S
/A
LT
_
R
ESET
/A
L
T
_D
CL
K
/A
LT
_DAT
A
/A
LT
_CONF_DONE
/A
LT
_CONFIG
HEAD_UD
P
INCHP
OS
R326
10K
R359
10K
R358
10K
R360
10K
R129
10K
P
C
100
CE
0.
1u
VCC3
TP
330
TP
325
TP
331
TP
326
TP
332
TP
327
TP
333
TP
328
TP
334
TP
329
T84
T87
T85
/CCS0
T78
T83
T89
T90
T77
T80
T86
T100
T74
T75
T112
T111
P
C
265
CE
0.
1u
P
C
116
CE0.
1u(NON)
R298
NON
T144
R297
NON
T148
T145
T151
T153
T150
T149
T154
T142
T76
R311
NON
R310
0
GND
A1
VCCIO2
A2
I/
O/
LVDS11p
A3
I/
O/
LVDS12p
A4
I/
O/
LVDS13p
A5
I/O/
LVDS19n
A7
I/O
A8
I/O/
LVDS17p
A6
I/O/
LVDS20n
A9
I/O/
LVDS23p
A10
I/O
A11
I/
O/
LVDS25p
A12
I/O/
LVDS26p
A13
I/
O/
LVDS28p
A14
VCCIO2
A15
GND
A16
VCCIO1
B1
GND
B2
I/
O/
LVDS11n
B3
I/
O/
LVDS12n
B4
I/
O/
LVDS13n
B5
I/
O/
LVDS17n
B6
I/O/
LVDS19p
B7
NC
B8
I/O/
LVDS20p
B9
I/O/
LVDS23n
B10
I/O
B11
I/
O/
LVDS25n
B12
I/
O/
LVDS26n
B13
I/
O/
LVDS28n
B14
GND
B15
VCCIO3
B16
I/O/CRC_E
RROR/L
VDS9p
C1
I/
O/
CLK
U
SR/
L
VDS9n
C2
I/
O/
ASDO
C3
I/
O/
LVDS14p
C4
I/
O/
LVDS14n
C5
I/
O/
LVDS15p
C6
VCCIO2
C7
GND
C8
GND
C9
VCCIO2
C10
I/O/
VREF
B2N0
C11
I/O/
LVDS27p
C12
I/
O/
LVDS27n
C13
I/
O/
LVDS29n
C14
NC
C15
NC
C16
NC
D1
NC
D2
I/
O/
LVDS6p
D3
I/
O/
LVDS6n
D4
I/
O/
LVDS8p
D5
I/
O/
LVDS15n
D6
NC
D7
I/O/
VREF
B2N1
D8
NC
D9
I/O/
LVDS21p
D10
I/O/
LVDS21n
D11
GND_P
LL2
D12
I/
O/
LVDS29p
D13
I/
O/
P
LL2_OUT
n
D14
I/O/
LVDS30n
D15
I/O/
LVDS30p
D16
I/O
E1
I/O
E2
I/
O/
LVDS7p
E3
I/
O/
LVDS7n
E4
I/
O/
LVDS8n
E5
I/
O/
LVDS10p
E6
VCCIO2
E7
GND
E8
GND
E9
VCCIO2
E10
GNDA_PLL
2
E11
VCCA_PLL2
E12
NC
E13
I/O/
PLL
2_OUTp
E14
NC
E15
I/O
E16
DATA0
F1
TCK
F2
I/O
F3
I/O/nCSO
F4
NC
F5
I/
O/
LVDS10n
F6
I/
O/
LVDS18n
F7
I/
O/
LVDS18p
F8
I/O/
LVDS22p
F9
I/O/
LVDS22n
F10
VCCD_PLL2
F11
GND_PLL
2
F12
NC
F13
NC
F14
I/
O/
LVDS33n
F15
I/
O/
LVDS33p
F16
TMS
G1
TDO
G2
VCCIO1
G3
NC
G4
nCE
G5
I/
O/
LVDS16n
G6
I/
O/
LVDS16p
G7
GND
G8
VCCINT
G9
I/O/
LVDS24n
G10
I/O/
LVDS24p
G11
I/
O/
LVDS31n
G12
I/
O/
LVDS31p
G13
VCCIO3
G14
I/
O/
LVDS34p
G15
I/
O/
LVDS34n
G16
CL
K
1
/L
VDSCL
K
0
n
H1
CL
K
0
/L
VDSCL
K
0
p
H2
GND
H3
DCLK
H4
TDI
H5
NC
H6
VCCINT
H7
GND
H8
GND
H9
VCCINT
H10
I/O/
LVDS32p
H11
I/O/
LVDS35n
H12
I/O/
VREF
B3N0
H13
GND
H14
CL
K
5
/L
VDSCL
K
2
n
H15
CLK4/
LVDSCL
K2p
H16
CL
K
3
/L
VDSCL
K
1
n
J1
CLK2/
LVDSCL
K1p
J2
GND
J3
I/O/
VREF
B1N1
J4
nCONFIG
J5
VCCINT
J7
GND
J8
NC
J6
GND
J9
NC
J1
0
I/O/
LVDS32n
J11
I/O/
LVDS35p
J12
MSEL0
J1
3
GND
J1
4
CL
K
6
/L
VDSCL
K
3
p
J1
5
CLK7/
LVDSCL
K3n
J16
I/O/
LVDS4n
K1
I/
O/
LVDS4p
K2
VCCIO1
K3
I/O/
LVDS3p
K4
I/
O/
LVDS3n
K5
NC
K6
NC
K7
NC
K8
GND
K9
I/
O/
LVDS48n
K1
0
I/O/
LVDS48p
K11
MSEL1
K1
2
NC
K1
3
VCCIO3
K1
4
I/O/
LVDS36p
K15
I/
O/
LVDS36n
K1
6
I/
O/
LVDS2p
L1
I/O/
LVDS2n
L2
I/O
L3
I/O/
PLL
1_OUTp
L4
GND_P
LL1
L5
VCCD_P
L
L
1
L6
I/
O/
LVDS60p
L7
I/
O/
LVDS60n
L8
I/
O/
LVDS50p
L9
I/
O/
LVDS50n
L1
0
I/O/
LVDS43n
L11
I/O
L12
CONF_DONE
L1
3
I/O
L14
I/O/
LVDS37n
L15
I/O/
LVDS37p
L16
I/O
M1
I/O
M2
I/O
M3
I/O/
PLL
1_OUTn
M4
VCCA_P
L
L
1
M5
GNDA_P
LL1
M6
VCCIO4
M7
GND
M8
GND
M9
VCCIO4
M10
I/O/
LVDS43p
M11
I/O/
LVDS42p
M12
nS
TA
TU
S
M13
I/O/
VREF
B3N1
M14
I/O/
LVDS38n
M15
I/O/
LVDS38p
M16
I/
O/
LVDS1p
N1
I/O/
LVDS1n
N2
NC
N3
NC
N4
GND_PLL
1
N5
NC
N6
NC
N7
I/
O/
VREFB4N1
N8
I/
O/
LVDS59p
N9
I/
O/
LVDS59n
N10
I/O/
VREF
B4N0
N11
I/O/
LVDS42n
N12
I/O/
LVDS41n/
INIT_DONE
N13
I/O/LVDS41p/nCEO
N14
I/O/
LVDS39n
N15
I/O/
LVDS39p
N16
I/
O/
LVDS0p
P1
I/O/
LVDS0n
P2
I/O
P3
I/
O/
LVDS57n
P4
I/O/
LVDS57p
P5
NC
P6
VCCIO4
P7
GND
P8
GND
P9
VCCIO4
P10
I/O
P11
I/O/
LVDS47p
P12
I/O/
LVDS47n
P13
I/O
P14
I/O/
LVDS40n
P15
I/O/
LVDS40p
P16
VCCIO1
R1
GND
R2
I/
O/
LVDS58n
R3
I/
O/
LVDS56n
R4
I/
O/
LVDS55n
R5
NC
R6
I/
O/
LVDS54n
R7
I/
O/
LVDS53n
R8
I/
O/
LVDS52n
R9
I/
O/
LVDS49p
R10
I/O/
LVDS51n
R11
I/O/
LVDS46n
R12
I/O/
LVDS45n
R13
I/O/
LVDS44n
R14
GND
R15
VCCIO3
R16
GND
T1
VCCIO4
T2
I/
O/
LVDS58p
T3
I/
O/
LVDS56p
T4
I/
O/
LVDS55p
T5
I/O
T6
I/
O/
LVDS54p
T7
I/
O/
LVDS53p
T8
I/
O/
LVDS52p
T9
I/
O/
LVDS49n
T10
I/O/
LVDS51p
T11
I/O/
LVDS46p
T12
I/O/
LVDS45p
T13
I/O/
LVDS44p
T14
VCCIO4
T15
GND
T16
IC36
EP2C5F256
5
5
4
4
6
6
3
3
7
7
2
2
8
8
1
1
RA73
E
X
BV8V103J
5
5
4
4
6
6
3
3
7
7
2
2
8
8
1
1
RA72
E
X
BV8V103J
R277
10K
R276
10K
/D
RE
Q
0
/D
RE
Q
0
1
2
3
4
5
10
9
8
7
6
RA74
E
X
BA10E
103J
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SW
1
KH
S
0
8
VCC3
EXT
_
IN
0
EXT
_
IN
1
EXT
_
IN
2
EXT
_
IN
3
EXT
_
OUT
0
EXT
_
OUT
1
EXT
_
OUT
2
EXT
_
OUT
3
EXT
_
OUT
2
EXT
_
OUT
1
EXT
_
OUT
0
EXT
_
IN
1
EXT
_
IN
0
EXT
_
IN
2
EXT
_
IN
3
EXT
_
OUT
3
T79
HEAD_SENS
HEAD_SENS
/CS5
/CS5
/CS
1
/CS
1
MA18
R303
10K
T123
VCC3
R304
10K
T133
R301
10K
T122
VCC3
m
ac_clk
m
ac_clk
R273
0(NON)
R279
10K
W
D
T
_
/OUT