± 2g / 4g / 8g / 16g Tri-axis Digital
Accelerometer Technical
Reference Manual
PART NUMBER:
KX132-1211
Rev. 1.0
31-Jul-2019
36 Thornwood Dr.
–
Ithaca, NY 14850
© 2019 Kionix
–
All Rights Reserved
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Page
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CNTL5
Control register 5. Read/write control register that provides more feature set control. This register is On-The-Fly (OTF)
register and can be written to while the KX132-1211
is enabled (PC1 bit in CNTL1 register is set to “1”) and the change
will be accepted with no interruption in the operation.
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reserved
Reserved
Reserved
ADPE
Reserved
Reserved MAN_WAKE MAN_SLEEP
Reset Value
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
00000000
Address:
0x1F
ADPE
–
Advanced Data Path (ADP) enable
ADPE = 0
– Advanced Data Path is disabled.
ADPE = 1
– Advanced Data Path is enabled. Outputs are available in XADP, YADP, ZADP
registers.
MAN_WAKE
–
manual wake-sleep engine overwrite
MAN_WAKE = 0
– default
MAN_WAKE = 1
– forces wake state (bit is self-cleared)
MAN_SLEEP
– manual wake-sleep engine overwrite
MAN_SLEEP = 0
– default
MAN_SLEEP = 1
– forces sleep state (bit is self-cleared)
Reserved
– these bits are reserved, and their values should not be changed.
Notes:
1. Once a wake interrupt has occurred, no additional wake interrupt events are registered until the
part is put back to sleep using the BTS interrupt or manually using MAN_SLEEP bit.
2. Wake is the default state at power-up, shown in STATUS_REG register. For wake engine only
operation, set MAN_SLEEP bit to 1 in CNTL5 register to put KX132-1211 in sleep state for the first
time.
