± 2g / 4g / 8g / 16g Tri-axis Digital
Accelerometer Technical
Reference Manual
PART NUMBER:
KX132-1211
Rev. 1.0
31-Jul-2019
36 Thornwood Dr.
–
Ithaca, NY 14850
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–
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Page
14
of
73
1.9
INTERRUPT SOURCE REGISTERS (0x16
– 0x18)
These three registers report interrupt state changes. The status is updated when a new interrupt event occurs, and the
bit remains set until it is cleared as indicated in each case.
INS1
This register contains Tap
TM
/Double-Tap
TM
axis specific interrupts. Data is updated at the ODR settings determined
by OTDT<2:0> in CNTL3. These bits are cleared when the interrupt latch release register (INT_REL) is read.
R
R
R
R
R
R
R
R
Reserved
Reserved
TLE
TRI
TDO
TUP
TFD
TFU
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Address:
0x16
Bit
Description
TLE
X Negative (X-) Reported
TRI
X Positive (X+) Reported
TDO
Y Negative (Y-) Reported
TUP
Y Positive (Y+) Reported
TFD
Z Negative (Z-) Reported
TFU
Z Positive (Z+) Reported
Table 4:
Directional-Tap
TM
Reporting
INS2
This register tells which function caused an interrupt.
R
R
R
R
R
R
R
R
FFS
BFI
WMI
DRDY
TDTS1
TDTS0
Reserved
TPS
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Address:
0x17
FFS
– Free fall Status (FFS) bit. This bit is cleared when the interrupt latch release register
(INT_REL) is read.
FFS = 0
– No Free fall
FFS = 1
– Free fall has activated the interrupt
BFI
– Buffer Full Interrupt (BFI) bit indicates that buffer has been filled. This bit is automatically
cleared when at least one sample from the buffer is read.
BFI = 0
– Buffer is not full
BFI = 1
– Buffer is full
