Rohm Kionix KX132-1211, Technical Reference Manual

Page: 6 / 73

± 2g / 4g / 8g / 16g Tri-axis Digital
Accelerometer Technical
Reference Manual
PART NUMBER:
KX132-1211
Rev. 1.0
31-Jul-2019
36 Thornwood Dr. – Ithaca, NY 14850 © 2019 Kionix – All Rights Reserved
tel: 607-257-1080 – fax:607-257-1146 893-12874-1907311402-0.17
www.kionix.com - info@kionix.com Page 6 of 73
1 Embedded Registers
1.1 Register Map
The KX132-1211 has embedded 8-bit registers that are accessible by the user. This section contains the addresses for
all embedded registers and describes bit functions of each register. Table
1
below provides a listing of the accessible
8-bit registers and their addresses.
Address Register Name R/W Address Register Name R/W Address Register Name R/W
00 MAN_ID R 1B CNTL1
1
R/W 33 FFC
2
R/W
01 PART_ID R 1C CNTL2
2
R/W 34 FFCNTL
1
R/W
02 XADP_L R 1D CNTL3
1
R/W 35-36 Kionix Reserved
3
03 XADP_H R 1E CNTL4
1
R/W 37 TILT_ANGLE_LL
2
R/W
04 YADP_L R 1F CNTL5
2
R/W 38 TILT_ANGLE_HL
2
R/W
05 YADP_H R 20 CNTL6
2
R/W 39 HYST_SET
2
R/W
06 ZADP_L R 21 ODCNTL
1
R/W 3A LP_CNTL1
1
R/W
07 ZADP_H R 22 INC1
1
R/W 3B LP_CNTL2
1
R/W
08 XOUT_L R 23 INC2
1
R/W 3C-48 Kionix Reserved
3
09 XOUT_H R 24 INC3
1
R/W 49 WUFTH
2
R/W
0A YOUT_L R 25 INC4
1
R/W 4A BTSWUFTH
2
R/W
0B YOUT_H R 26 INC5
1
R/W 4B BTSTH
2
R/W
0C ZOUT_L R 27 INC6
1
R/W 4C BTSC
2
R/W
0D ZOUT_H R 28 Kionix Reserved
3
4D WUFC
2
R/W
0E-11 Kionix Reserved
3
29 TILT_TIMER
2
R/W 4E-5C Kionix Reserved
3
12 COTR R 2A TDTRC
2
R/W 5D SELF_TEST W
13 WHO_AM_I R 2B TDTC
2
R/W 5E BUF_CNTL1
2
R/W
14 TSCP R 2C TTH
2
R/W 5F BUF_CNTL2
2
R/W
15 TSPP R 2D TTL
2
R/W 60 BUF_STATUS_1 R
16 INS1 R 2E FTD
2
R/W 61 BUF_STATUS_2 R
17 INS2 R 2F STD
2
R/W 62 BUF_CLEAR
2
W
18 INS3 R 30 TLT
2
R/W 63 BUF_READ R
19 STATUS_REG R 31 TWS
2
R/W 64-76 ADP_CNTL(1-19)
2
R/W
1A INT_REL R 32 FFTH
2
R/W 77-7F Kionix Reserved
3
Table 1: Register Map
Notes
1. When changing the contents of these registers, the PC1 bit in CNTL1 must first be set to
“0”.
2. On-The-Fly (OTF) register can be written to while the KX132-1211 is enabled (PC1 bit in
CNTL1 register is 1) and the change will be accepted with no interruption in the operation.
3. Reserved registers should not be written.