± 2g / 4g / 8g / 16g Tri-axis Digital
Accelerometer Technical
Reference Manual
PART NUMBER:
KX132-1211
Rev. 1.0
31-Jul-2019
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–
Ithaca, NY 14850
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Page
27
of
73
1.14 INTERRUPT CONTROL REGISTERS (0X22
– 0X27)
INC1
Interrupt Control 1. This register controls the settings for the physical interrupt pin INT1. Note that to properly change
the value of this register, the PC1 bit in CNTL1 register
must first be set to “0”.
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PW11
PW10
IEN1
IEA1
IEL1
Reserved
STPOL
SPI3E
Reset Value
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
00010000
Address:
0x22
PW1<1:0>
– Pulse INT1 pin width configuration
00 = 50µsec (10µsec if accelerometer ODR (OSA<3:0>) > 1600Hz)
01 = 1 * OSA period
10 = 2 * OSA periods
11 = Real time mode
When PW1 > 0, Interrupt source auto-clearing (ACLR1=1) should be set to keep consistency
between the internal status and the physical interrupt.
IEN1
– enables/disables the physical interrupt pin
IEN1 = 0
– physical interrupt pin is disabled
IEN1 = 1
– physical interrupt pin is enabled
IEA1
– Interrupt active level control for interrupt pin
IEA1 = 0
– active LOW
IEA1 = 1
– active HIGH
IEL1
– Interrupt latch control for physical interrupt pin
IEL1 = 0
– latched until cleared by reading INT_REL
IEL1 = 1
– pulsed. The pulse width is configurable by PW1.
Reserved
– this bit is reserved, and its value should not be changed.
STPOL
– sets the polarity of Self-Test.
STPOL = 0
– Negative
STPOL = 1
– Positive
SPI3E
– sets the 3-wire SPI interface
SPI3E = 0
– disabled
SPI3E = 1
– enabled
