Rohm Kionix KX132-1211, Technical Reference Manual

Page: 35 / 73

± 2g / 4g / 8g / 16g Tri-axis Digital
Accelerometer Technical
Reference Manual
PART NUMBER:
KX132-1211
Rev. 1.0
31-Jul-2019
36 Thornwood Dr. – Ithaca, NY 14850 © 2019 Kionix – All Rights Reserved
tel: 607-257-1080 – fax:607-257-1146 893-12874-1907311402-0.17
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FTD
This register contains counter information for the detection of any tap event. When the Directional-Tap
TM
ODR is 400Hz
or less, every count is calculated as 1/ODR delay period. When the Directional-Tap
TM
ODR is 800Hz, every count is
calculated as 2/ODR delay period. When the Directional-Tap
TM
ODR is 1600Hz, every count is calculated as 4/ODR
delay period. The Directional-Tap
TM
ODR is user-defined per Table 10. To ensure that only tap events are detected,
these time limits are used. A tap event must be above the performance index threshold for at least the low limit (FTDL0
– FTDL2) and no more than the high limit (FTDH0 – FTDH4). The Kionix recommended default value for the high limit
is 0.05 seconds and for the low limit is 0.005 seconds (0xA2).
R/W R/W R/W R/W R/W R/W R/W R/W
FTDH4 FTDH3 FTDH2 FTDH1 FTDH0 FTDL2 FTDL1 FTDL0 Reset Value
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 10100010
Address: 0x2E
STD
This register contains counter information for the detection of a double tap event. When the Directional-Tap
TM
ODR is
400Hz or less, every count is calculated as 1/ODR delay period. When the Directional-Tap
TM
ODR is 800Hz, every
count is calculated as 2/ODR delay period. When the Directional-Tap TM ODR is 1600Hz, every count is calculated as
4/ODR delay period. The Directional-Tap
TM
ODR is user-defined per Table 10. To ensure that only tap events are
detected, this time limit is used. This register sets the total amount of time that the two taps in a double tap event can
be above the PI threshold (TTL). The Kionix recommended default value for STD is 0.09 seconds (0x24).
R/W R/W R/W R/W R/W R/W R/W R/W
STD7 STD6 STD5 STD4 STD3 STD2 STD1 STD0 Reset Value
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 00100100
Address: 0x2F
TLT
This register contains counter information for the detection of a tap event. When the Directional-Tap
TM
ODR is 400Hz
or less, every count is calculated as 1/ODR delay period. When the Directional-Tap
TM
ODR is 800Hz, every count is
calculated as 2/ODR delay period. When the Directional-Tap TM ODR is 1600Hz, every count is calculated as 4/ODR
delay period. The Directional-Tap TM ODR is user-defined per Table 10. To ensure that only tap events are detected,
this time limit is used. This register sets the total amount of time that the tap algorithm will count samples that are above
the PI threshold (TTL) during a potential tap event. It is used during both single and double tap events. However,
reporting of single taps on the physical interrupt pin INT1 or INT2 will occur at the end of the TWS. The Kionix
recommended default value for TLT (TDT Latency Timer) is 0.1 seconds (0x28).
R/W R/W R/W R/W R/W R/W R/W R/W
TLT7 TLT6 TLT5 TLT4 TLT3 TLT2 TLT1 TLT0 Reset Value
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 00101000
Address: 0x30