± 2g / 4g / 8g / 16g Tri-axis Digital
Accelerometer Technical
Reference Manual
PART NUMBER:
KX132-1211
Rev. 1.0
31-Jul-2019
36 Thornwood Dr.
–
Ithaca, NY 14850
© 2019 Kionix
–
All Rights Reserved
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Page
33
of
73
1.15 TILT_TIMER (0X29)
Initial count register for the tilt position state timer (0 to 255 counts). Every count is calculated as 1/ODR delay period,
where the ODR is user-defined per Table 9. The sensor must remain for the duration of the timer count in the new tilt
position before the change is accepted. This register is On-The-Fly (OTF) register and can be written to while the
KX132-1211
is enabled (PC1 bit in CNTL1 register is set to “1”) and the change will be accepted with no interruption in
the operation.
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
TSC7
TSC6
TSC5
TSC4
TSC3
TSC2
TSC1
TSC0
Reset Value
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
00000000
Address:
0x29
1.16 TAP / DOUBLE-TAP CONTROL REGISTERS (0x2A
– 0x31)
The Tap
TM
/Double-Tap
TM
engine is enabled with TDTE bit in CNTL1 register and can be configured via dedicated set
of control registers 0x2A
Directional-Tap Detection Feature Description
section for detailed
information on the Tap
TM
/Double-Tap
TM
engine. These registers are On-The-Fly (OTF) registers and can be written to
while the KX132-1211
is enabled (PC1 bit in CNTL1 register is set to “1”) and the change will be accepted with no
interruption in the operation.
TDTRC
Tap
TM
/Double-Tap
TM
Report Control.
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
DTRE
STRE
Reset Value
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
00000011
Address:
0x2A
DTRE
– enables/disables the double tap interrupt
DTRE = 0
– do not update INS1 or DTDS if double tap occurs
DTRE = 1
– update INS1 and DTDS in INS2 with double tap events
STRE
– enables/disables single tap interrupt
STRE = 0
– do not update INS1 or DTDS if single tap occurs.
STRE = 1
– update INS1 and DTDS in INS2 single tap events
