± 2g / 4g / 8g / 16g Tri-axis Digital
Accelerometer Technical
Reference Manual
PART NUMBER:
KX132-1211
Rev. 1.0
31-Jul-2019
36 Thornwood Dr.
–
Ithaca, NY 14850
© 2019 Kionix
–
All Rights Reserved
tel: 607-257-1080 – fax:607-257-1146
893-12874-1907311402-0.17
www.kionix.com -
Page
45
of
73
1.24 ADVANCED DATA PATH CONTROL REGISTERS (0x64
– 0x76)
The advanced data path (ADP) engine of the KX132-1211 can be configured via control registers 0x64
– 0x76 shown
below. The ADP engine is enabled by setting ADPE bit to 1 in CNTL5 register. The ADP output data can be routed to
the output registers 0x02
– 0x07, and/or to the sample buffer. See
AN097 Getting Started with Advanced Data Path
for
more information about recommended register setup. These registers are On-The-Fly (OTF) registers and can be
written to while the KX132-1211
is enabled (PC1 bit in CNTL1 register is set to “1”) and the change will be accepted
with no interruption in the operation.
ADP_CNTL1
Advanced Data Path (ADP) Output Control register 1.
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reserved RMS_AVC2 RMS_AVC1 RMS_AVC0
OADP3
OADP2
OADP1
OADP0
Reset Value
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
00000000
Address:
0x64
Reserved
– this bit is reserved, and its value should not be changed.
RMS_AVC<2:0>
– Number of samples used to calculate RMS output. Each sample is determined by
the Advanced Data Path ODR as set by OADP<3:0> bits.
Note 1: If ADP data is routed to the Wake-up / Back-to-Sleep engines, RMS_AVC<2:0> also
sets the number of samples averaged for these engines.
Note 2: The input data to the Advanced Data Path is first averaged per AVC<2:0> setting in
LP_CNTL1 (0X3A) register.
000 = 2 samples
100 = 32 samples
001 = 4 samples
101 = 64 samples
010 = 8 samples
110 = 128 samples
011 = 16 samples
111 = 256 samples
OADP<3:0>
– Output Data Rate (ODR) for Advanced Data Path. For filter-1 and filter-2 stages, the
ODR set by OADP<3:0> is the effective ODR. For RMS block the effective ODR is scaled down
by RMS_AVC<2:0> setting.
Note 1: If ADP data is routed to the Wake-up / Back-to-Sleep engines, OADP<3:0> also sets
the ODR for these engines.
Note 2: OADP setting needs to be ≤OSA to avoid irregular resulting acceleration ODRs.
0000 = 0.781Hz
1000 = 200Hz
0001 = 1.563Hz
1001 = 400Hz*
0010 = 3.125Hz
1010 = 800Hz*
0011 = 6.25Hz
1011 = 1600Hz*
0100 = 12.5Hz
1100 = 3200Hz*
0101 = 25Hz
1101 = 6400Hz*
0110 = 50Hz
1110 = 12800Hz*
0111 = 100Hz
1111 = 25600Hz*
* Higher ODR values will increase the power consumption of the sensor.
