± 2g / 4g / 8g / 16g Tri-axis Digital
Accelerometer Technical
Reference Manual
PART NUMBER:
KX132-1211
Rev. 1.0
31-Jul-2019
36 Thornwood Dr.
–
Ithaca, NY 14850
© 2019 Kionix
–
All Rights Reserved
tel: 607-257-1080 – fax:607-257-1146
893-12874-1907311402-0.17
www.kionix.com -
Page
25
of
73
1.13 ODCNTL (0X21)
Output data control register that configures the acceleration outputs. Note that to properly change the value of these
registers, the PC1 bit in CNTL1 register must first be set to “0”.
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
IIR_BYPASS
LPRO
FSTUP
Reserved
OSA3
OSA2
OSA1
OSA0
Reset Value
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
00000110
Address:
0x21
IIR_BYPASS
– IIR Filter Bypass mode enable bit
IIR_BYPASS = 0
– IIR filter is not bypassed, i.e. filtering is applied (default)
IIR_BYPASS = 1
– IIR filter is bypassed.
Notes for IIR_BYPASS = 1 setting:
1. Not recommended at OSA<3:0> = 1111 (ODR = 25600Hz)
2. Not recommended in Low Power Mode with AVC<2:0> = 000 setting (no
averaging)
3. This setting may reduce the resolution of the output data.
LPRO
– Low-Pass filter Roll-Off control
LPRO = 0
– IIR filter corner frequency set to ODR/9 (default)
LPRO = 1
– IIR filter corner frequency set to ODR/2
Figure 1:
Low-Pass Filter Design and Control Circuitry
